Abstract: A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level.

Abstract: A system and method for obtaining the bearing angle of radio frequency is utilized in a direction finding system to determine the signal of interest. The system utilized an adaptive interferometric processor to null out modulation occurring due to commutation between the antenna elements. Through this system the bearing angle can be determined accurately and efficiently.

Abstract: An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

Abstract: An input buffer circuit is provided that has improved speed performance. The input buffer circuit has a voltage swing of V.sub.DD -V.sub.th to V.sub.SS. In so doing, the speed of the input buffer signal from input to output is significantly increased. In addition, the circuit also incorporates an additional current leaker transistor that limits the output high voltage from going above V.sub.DD -V.sub.th.

Abstract: A low voltage charge pump operable with a low voltage power supply and a clock signal is provided for delivering a final output voltage which is higher than the supply voltage. The low voltage charge pump comprises MOS capacitors formed of MOS devices, each capacitor including a p-well acting as a plate of the respective capacitor. Through this arrangement, the effective area of the capacitor is increased resulting in an increase in capacitance. Therefore, a more efficient charge pumping effect is provided in a low voltage power supply such as 3.3 volts. The p-well of each of the capacitor is driven from ground voltage to one threshold voltage less than the supply voltage to minimize forward bias of the p-wells and the n-type substrates of the MOS devices.

Abstract: A high performance hermetic integrated circuit package assembly for housing an integrated circuit die wherein the package assembly affords substantially reduced ground bounce within the integrated circuit. The package assembly includes a lead frame of electrically conductive material having a first predetermined pattern of outer leads and a second predetermined pattern of, integrally connected, inner leads for providing interconnection to the die through a plurality of contact pads thereon, a series of electrically conductive wires connecting selected ones of the contact pads to selected ones of the inner leads, a base for mounting the die and includes a first layer of glass for supporting the lead frame and, a cap with a second layer of glass for reacting with the first layer of glass to provide a hermetic enclosure for the die.

Abstract: A system is disclosed that allows a computer system within a network environment to determine whether a data packet is to be processed by a particular computer system. This is accomplished through an address matching scheme that provides for an LED indication that the computer is to utilize the data packet provided by the network. In so doing, the system provides more capability to the computers on a network to operate more efficiently.

Abstract: A method and apparatus for storing and retrieving multi-dimensional data in which a multi-level data structure is defined wherein one level contains those dimensions chosen by the user to result in dense data and the other level contains the remaining sparse data combinations. The dense dimensions specified in any given case are used to determine the basic block size used to store information. The remaining sparse dimensions are used to create the upper level structure which is used to point to the block which contains the desired information. Depending upon the sparseness of the data, different types of upper level structure may be used. Both the variable data block size and the choice of pointer structure may be used to balance the memory required against the speed of retrieval.

Abstract: An output buffer circuit is disclosed that minimizes signal oscillation or ringing on a data bus while limiting the power dissipated. This circuit includes a pair of reference voltage generators which provide clamp voltages that limit the signal oscillation and a mechanism for shutting down the appropriate generator when it is not operating. The output buffer circuit has the capability of driving the output transistors to their CMOS levels in order to maximize the sinking and sourcing currents.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.

Abstract: A secondary cache control system for a computer system is disclosed. The system is utilized advantageously to reduce the cost of the SRAM while not degrading the overall performance of the CPU associated with the computer. The system latches the data from the CPU until the CPU hits a "dead time". When this dead time occurs, the data is written into the SRAM. By writing to the SRAM at this time the performance of the computer system is not degraded and the cost of the SRAM is significantly reduced.

Abstract: A system for adjusting the synchronizing signal received by an ENDEC receiver in a token ring network is disclosed. The system used lookahead logic in conjunction with the packet delimiter byte to adjust the synchronizing signal without delaying any bits received by the ENDEC receiver. This system has significant utility in Fiber Distributed Data Interface (FDDI) networks.

Abstract: A method and apparatus for accessing a color palette in a color graphics system synchronously and asynchronously. Address and data registers coupled to the color palette are operated synchronously in a pipeline fashion using clock pulses having a pixel scanning rate when the palette is used for refreshing a color monitor. The address and data registers are operated asynchronously, i.e. rendered transparent to addresses and data, respectively, when the palette is updated by a CPU.

Abstract: This regulating system for an array of solar panels or the like consists of a tap connection into the array, and a boost switching regulator connected to the tapped array. The tap connection divides the array into first and second portions, and the switching regulator is connected so that its power-input terminals are across only one of the two portions of the array. The power-output terminals of the switching regulator are connected across the load (i.e., across the entire array), and the sensing or feedback terminals of the regulator receive a signal which acts as a measure of voltage or current at the load.Boost regulators do not dump overvoltage into a dissipative load; hence the invention prevents local heat generation and resulting spacecraft heat-balance problems of conventional dissipative regulators.

Abstract: A phase compensated waveguide hybrid coupler is formed with a pair of waveguides of rectangular cross section and sharing a common short wall. An aperture in the short wall provides for the coupling of electromagnetic energy between a first of the waveguides and a second of the waveguides. Such coupling introduces a 90.degree. phase shift. An input terminal is located at an end of the first waveguide. Phase compensation is introduced by a set of capacitive irises located in the first waveguide and by a set of inductive irises located in the second waveguide. The capacitive and inductive irises are located on a side of said coupling aperture away from said input terminal.

Abstract: A microwave resonator is disclosed which includes a temperature-compensating structure within the resonator cavity configured to undergo temperature-induced dimensional changes which substantially minimize the resonant frequency change otherwise caused by temperature-induced changes in the waveguide body cavity. The temperature-compensating structure includes both bowed and cantilevered structures on the cavity endwall, as well as structures on the cavity sidewall such as a tuning screw of temperature-responsive varying diameter.

Abstract: An electronic postage meter includes electronic circuitry for providing an accounting of the number of mailpieces imprinted with postage, and the amount of postage imprinted on such mailpieces. An electro-optic sensor connects with a mechanical drive of a printing drum of the meter to sense successive rotations of the printing drum, one rotation occurring for each imprinting of postage. A comparison circuit compares the one-bit signal provided by the electro-optic sensor with the least significant bit of a count of the mailpieces, which count is provided electronically by the accounting function. Any discrepancy between the least significant bit of the mechanical count and the least significant bit of the electronic count serves as a warning of a malfunction, or of tampering, of the postage unit. An error-signal circuit connected to the comparison circuit terminates operation of the meter upon the occurrence of a discrepancy between the mechanical and electrical counts.

Abstract: Method and apparatus for initializing the printwheels in an electronic postage meter is disclosed. The apparatus comprises a printwheel selection mechanism which is comprised of various components. The various components on the printwheel selection mechanism are adjusted to set a plurality of printwheels to a predetermined position. After those printwheels are adjusted a signal is produced which indicates that the printwheels are located at that predetermined position. The various components of the printwheel selection mechanism are sequentially adjusted to set the printwheels so that the postage meter settings are at a known initial point.