Abstract: A data stream received by a hard disk drive (HDD) is organized into at least one cluster having data blocks and spare data blocks and that is equal in size to an integer multiple of the number of sectors in a track of a disk of the HDD. A variable-index writing technique is used to write each data block of a cluster to a corresponding sector of a track that is encountered by a head when the sector is not defective. A sector of the track is skipped during writing when the sector is defective. The number of spare data blocks in a portion of a cluster corresponding to a single track is reduced by the number of sectors that are skipped in the track so that the number of data blocks plus the number of remaining spare data blocks equals the number of sectors in a track.

Abstract: A floating symmetrical current limiter device blocks large bipolar input signals to the input circuit of an instrumentation device by transitioning between a low-impedance mode and a high-impedance mode. The current limiter device includes a signal path and a control path that are each coupled between an input terminal and an output terminal. The signal path has a low impedance that passes small differential signals across the limiter from the input terminal to the output terminal. The control path is responsive to large bipolar signals that appear across the limiter terminals by transitioning between a voltage divider and a constant-current source-based bias that controls the impedance of the signal path to become a large impedance, thereby blocking the large bipolar input signal from the output terminal.

Abstract: A write-inhibit signal is generated by a head-disk interaction sensor during a write process that is integrated with a suspension of a hard disk drive (HDD) when fly-height modulation of the slider is detected during a write process The suspension load beam includes a dimple and a laminated flexure. The laminated flexure includes a surface that is adapted to receive a slider and a surface that is adapted to contact the dimple. The head-disk interaction sensor is fabricated as part of the laminations of the flexure. The head-disk interaction sensor can be an accelerometer that senses an acceleration of the flexure when the slider contacts the disk of the disk drive and/or a pressure sensor that senses a pressure between the flexure and the dimple when the slider contacts the disk. A write-inhibit circuit is responsive to the sensor signal by inhibiting the write process.

Abstract: A control system for an actuator arm assembly of a hard disk drive reduces the Non-Repeatable Run-out (NRRO) caused from external sources exciting higher-frequency actuator arm assembly modes. The actuator arm assembly includes a primary actuator and a secondary actuator. The control system includes a primary control loop controlling the primary actuator and a secondary control loop controlling the secondary actuator. The secondary control loop includes at least one peak filter at a frequency corresponding to at least one frequency that is greater in frequency than the primary mode of the actuator arm assembly. The primary actuator can be any type of primary actuator. Similarly, the secondary actuator can be any type of actuator that is located between the primary actuator and a read/write head.

Abstract: The performance capability of different heads that are part of the same hard disk drive (HDD) are utilized by an adaptive format that includes a plurality of storage zones and at least one reset zone that are distributed along a radius of the hard disk such that a reset zone is disposed between two adjacent storage zones. Each storage zone has a plurality of associated data tracks and each reset zone includes a plurality of data tracks. The number of data tracks associated with each respective storage zone is based on a performance capability of a head associated with the hard disk and includes at least one data track of at least one reset zone adjacent to the storage zone when the number of data tracks associated with the storage zone exceeds the number of data tracks that are between each reset zone adjacent to the storage zone.

Abstract: An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere.

Abstract: A metal induced crystallization process is provided which employs an amorphous silicon film precursor deposited by physical vapor deposition, wherein the precursor film does not readily undergo crystallization by partial solid phase crystallization. Using this physical vapor deposition amorphous silicon precursor film, the amorphous silicon film is transformed to polysilicon by metal induced crystallization wherein the crystalline growth occurs fastest at regions that have been augmented with a metal catalyst and proceeds extremely slowly, practically zero, at regions which bear no metal catalyst. Accordingly, by use of the physical vapor deposition amorphous silicon precursor film in the process of the present invention, the metal induced crystallization process may take place at higher annealing temperatures and shorter annealing times without solid phase crystallization taking place.

Abstract: A memory device formed from selectively deposited PGO and a method for selectively forming a Pb5Ge3O11 (PGO) thin film memory device are provided. The method comprises: forming a silicon (Si) substrate; forming a silicon oxide film overlying the substrate; forming a patterned bottom electrode overlying the silicon oxide film; selectively depositing a PGO film overlying the bottom electrode; annealing; and, forming a top electrode overlying the PGO film. Selectively depositing a PGO film overlying the bottom electrodes includes: depositing a seed layer of PGO; and, forming a c-axis oriented PGO layer overlying the seed layer.

Abstract: A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.

Abstract: A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided in the sputtering chamber. The sputtering power and oxygen partial pressure within the chamber is set to deposit a film comprising niobium monoxide, without excess amounts of elemental niobium, NbO2 insulator, or Nb2O5 insulator. The deposition method may be incorporated into a standard CMOS fabrication process, or a replacement gate CMOS process.

Abstract: A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. A gate is formed overlying the polycrystalline film. The polycrystalline film is doped to produce source and drain regions.

Abstract: A 1:1 laser projection system and method are provided for laser irradiating a semiconductor film. The method comprises: exposing a mask to a beam of laser light; projecting laser light passed through the mask by a factor of one; exposing the area of a semiconductor film to the projected laser light having a first energy density; exposing an area of semiconductor film to a lamp light having a second energy density; and, summing the first and second energy densities to heat the area of film. When the semiconductor film is silicon, the film heating typically entails melting, and then, crystallizing the film. In some aspects of the method, the lamp is an excimer lamp having a wavelength of less than 550 nanometers (nm), and the laser is an excimer laser having a wavelength of less than 550 nm. In some aspects, the lamp is mounted to expose the bottom surface of the film including an area underlying the area being laser irradiated.

Abstract: A method for write-precompensating a waveform for magnetically recording a waveform on a magnetic medium is disclosed. A user data stream is encoded into an encoded data stream so that the encoded data stream has no tribits and no consecutive dibits. No delay is applied to a first transition of a dibit of the encoded data stream. An isolated transition of the encoded data stream is delayed by a first predetermined amount of time. The second transition of a dibit of the encoded data stream is delayed by a second predetermined amount of time, such that the second predetermined amount of time is substantially twice the first predetermined amount of time. Preferably, the encoded data stream satisfies a predetermined run length limited (RLL) k− constraint of k=13 and a predetermined twins t-constraint of t=15. In one embodiment, the encoded data stream is encoded by a block code at rate 8:10. In another embodiment, the encoded data stream is encoded by a block code at rate 16:19.

Abstract: A device connected to an interface has operational logic and power control logic. The device further has multiple power modes, including a first mode and a second, lower power mode. In the first mode, the operational logic is coupled to the interface, and is able to communicate over the interface. In the second mode, the power control logic is coupled to the interface, and the operational logic is decoupled, and substantially powered down. This provides a low interface power mode. In this mode, the power control logic monitors the interface for command activity. The power control logic returns the device to the first mode when the device must be in the first mode to process or reply to the command. The power control logic thus provides for the restoration of function from a low interface power mode without the need for a special “wake-up” command, thereby making the low interface power mode transparent to the host.

Abstract: A method for forming a termination for a magnetic write head in which a magnetic write coil having an inner turn and an outer turn is formed on a wafer. A bottom capacitor plate for a capacitor on the wafer. A resistor having a first terminal and a second terminal is also formed on the wafer. A dielectric layer is formed over the bottom capacitor plate for the capacitor. A top capacitor plate is formed on the dielectric layer. An overpass lead is formed between the inner turn of the coil and one of the bottom capacitor plate and the top capacitor plate. The first terminal of resistor is connected to the capacitor plate that is not connected to the inner turn of the write coil. The second terminal of the resistor is connected to the outer turn of the write coil. An impedance formed by the write coil, the capacitor and the resistor substantially equals a characteristic impedance Z0 of an interconnect circuit that will be connected to the write coil.