Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract: Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

Abstract: The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: Content-addressable memory (CAM) cells comprised of phase change material devices (PCMDs), including PCMD-based binary CAM cells (PCMD-based BCAM cells), PCMD-based ternary CAM cells (PCMD-based TCAM cells), and PCMD-based universal CAM cells (PCMD-based UCAM cells). The PCMDs of the various PCMD-based CAM cells are configured and programmed in a manner that allows a logic “0” or a logic “1” to be stored by the CAM cell. The logic value stored by a given PCMD-based CAM cell depends on the program states of the PCMDs. A program state of a PCMD is determined by whether the phase change material of the PCMD has been allowed to solidify to a crystalline, low-resistance state during a programming operation, or whether the phase change material of the PCMD is forced to solidify to an amorphous, high-resistance state during the programming operation.

Abstract: Systems and methods for providing autonomous security are configured to modify an original header associated with an original data packet wherein key information is added; encrypt original data associated with the original data packet in response to the key information; and form an encrypted data packet including the modified header and the encrypted data, wherein the encrypted data packet is a same size as the original data packet.