Abstract: A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etching. The common mask defines an patterned oxide layer which includes a plurality of openings at a predetermined distance away from the scribe line of the MOSFET structure. During fabrication, material of the body layer is implanted through the openings of the patterned oxide layer. Thereafter, the implanted material is side-diffused and merged together under a drive-in cycle as one continuous body layer. Using the same patterned oxide layer as a shield, trenches are anisotropically etched in the substrate. The MOSFET structure as formed requires no separate mask for delineating the active body region away from the scribe line, resulting reduction of fabrication steps. The consequential benefits are lower manufacturing costs and higher production yields.

Abstract: A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.

Abstract: A non-volatile semiconductor memory cell includes a semiconductor substrate with a source and a drain formed therein. A channel is defined between the source and the drain. Atop the channel is a floating gate which is controlled by the X-control line and the Y-control line. The floating gate is uniquely disposed in the semiconductor substrate relative to the control lines such that when it is not addressed, the memory cell is isolated from the rest of the memory cells. As a consequence, the normal programming, deprogramming, and reading operations with other cells are not interfered. Moreover, the unique structure also facilitates the addressing of each of the memory cell.

Abstract: A power semiconductor device having internal circuits characterized by an electrical breakdown during one mode of operation is implemented with a protective circuit. The electrical breakdown is controllably induced to occur at the protective circuit thereby diverting any breakdown in the active circuits. In the preferred embodiment, the power device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the protective circuit is deposited as an annular diffusion ring having a shallow portion and a deep portion. The deep portion is higher in doping concentration than the shallow portion and includes a radius of curvature larger than the shallow portion. The radius of curvature of the deep portion can be adjusted to induce breakdown at or above the rated value of the MOSFET. The predetermined doping concentration of the deep portion can abort the breakdown prematurely to occur at the deep region instead of at the active circuits.

Abstract: A non-volatile semiconductor memory device for NAND application is described herein. The device comprises three layers of polysilicon with the first layer used as Y-control gate and second layer used as floating gate and the third layer used as X-control gate. The device has a high gate capacitance coupling ratio. In an array, the device can be programmed and erased randomly without being limited in a serial fashion.

Abstract: Conductive feed-throughs formed by partially migrating conductive material in a body of semiconductor material are used to provide electrical interconnections between the semiconductor surfaces. In addition, the conductive feed-throughs furnish mechanical support and thermal dissipation paths for the body of semiconductor material.

Abstract: Methods and structures of an etched-back thermomigrated interconnection which provides means for electrically connecting coplanar surfaces of a body of semiconductor material while concurrently providing means of making mechanical, electrical, and thermal external connections to the body of semiconductor material.

Abstract: A programmable interconnection of an integrated circuit including a floating gate having a portion thereof sandwiched in between a X-control trace and a Y-control trace. Another portion of the floating gate is dielectrically disposed atop the channel of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Electrical charges are couplingly induced in the floating gate through the Fowler-Nordheim (F-N) tunneling effect when both the X-control and Y-control traces are simultaneously energized. When the X-control trace and the Y-control trace are deenergized, the charged floating gate couplingly vary the electrical conductivity of the underlying channel, allowing the programmable interconnection to be programmed to be at the "connect" or "disconnect" states. A plurality of such programmable interconnections can also be arranged in the semiconductor substrate in a matrix of rows and columns for the ease of addressing.

Abstract: A non-volatile semiconductor memory cell includes a floating gate dielectrically disposed between a first and a second control gate. The non-volatile memory cell can only be addressed for programming or deprogramming by the simultaneous energization of the first and second control gates. With this unique feature, any memory cell in an memory array can be randomly accessed. Moreover, the two control gates associated with each of the floating gate also increase the coupling capacitances, thereby speeding up operations. The non-volatile memory device of the present invention is ideal to be used for large scale integration applications in which memory cells are arranged in a NAND structure.

Abstract: Non-volatile semiconductor memory integrated circuits which partition a main memory array into sub-arrays. Address lines of the main memory array are also partitioned into four groups. The first group and the second group are dedicated for the addressing of the sub-arrays. Each of the sub-arrays can be addressed by a simultaneous energization of a pair of address lines selected from the first and the second group. The third group and the fourth group are used for the addressing for individual memory cells in the sub-arrays. The simultaneous energization of a pair of address lines selected from the third and the fourth group can address any of the memory cells within a selected sub-array. The memory circuits of the present invention are applicable for memory cells with four terminals. In a first embodiment of the invention, the memory circuit is a one-bit wide circuit.

Abstract: A non-volatile semiconductor memory cell comprises a P-type semiconductor substrate (5) and N+ diffusion regions (6) spaced apart from each other on the principal surface of a P-type substrate (5). Each N+ diffusion region (6) can be used as source or drain of a transistor. Between any two adjacent N+ diffusion regions and under the gates is located the channel region (7). A control Y gate (8) is formed on an insulation layer above a portion of the channel and extends over a portion of N+ diffusion region (6). A floating gate (9) is formed on an insulation layer above the control Y gate (8) and the rest of the channel, and extends over a portion of another N+ diffusion region (6). A control X gate (10) is formed on an insulation layer above the floating gate (9) and N+ diffusion regions (6).

Abstract: A Read-Only semiconductor memory cell includes: a semiconductor substrate and a source and a drain formed on one surface of the substrate; a channel region, which is in between source and drain regions on the surface of the substrate, is controlled by X-control gate XCG and Y-control gate YCG which are formed on the surface of the substrate and isolated from each other and from source and drain regions and from semiconductor substrate through insulating films. Multiple levels of threshold voltages of the cells exist for ROM codes. The cell structure provide a means for accurate cell current during read, and is simpler for peripheral control circuit design and is contactless, fieldless, suitable for high reliable Mega-bit memory devices.

Abstract: A dual passage valve with four way controls comprises a synchronized poppet combination reciprocally mounted within the valve housing. There is a bore axially formed in the housing with two fluid passageways located at the proximal and distal ends of the bore. There are also inlet and outlet ports formed in the housing with the inlet port extending radially from the bore, and the outlet port having conduits extending into the two fluid passageways. The synchronized poppet combination selectively encloses and opens the bore to the two passageways allowing fluid to traverse through, stops at, and reverse from the valve synchronously in a one-stroke linear motion within the bore. The synchronized poppet combination distinctively dictates the fluid flow traffic and strictly forbids any disorderly fluid flow states within the valve.