Abstract: An apparatus and method for training the sensory perceptual system in a language learning impaired (LLI) subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by an LLI subject, and gradually improves the subject's neurological processing of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's temporal processing of acoustic events common to speech are significantly improved.

Abstract: An apparatus and method for training the sensory perceptual system in a language learning impaired (LLI) subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by an LLI subject, and gradually improves the subject's neurological processing of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's temporal processing of acoustic events common to speech are significantly improved.

Abstract: A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC.sub.-- CLK) signal and a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC.sub.-- SYN.sub.-- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC.sub.-- SYN.sub.-- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC.sub.-- SYN.sub.-- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle.

Abstract: A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with a tap coupled to the interconnect. Data is transferred from the host processor to the memory in the form of data packets. First, the host processor writes to the memory by sending a data packet to the primary memory controller which then caches the data from the data packet. The backup memory controller taps the interconnect to obtain a backup copy of the data packet as the data packet is being sent from the host processor to the primary memory controller which caches the data from the backup copy of the data packet. If the primary memory controller is functional, the primary memory controller sends the data to the memory via a primary path coupling the primary memory controller to the memory. Conversely, if the primary memory controller fails, i.e.

Abstract: A Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a cache (2,4) connected to the processor, in which the cache (2,4) is arranged to fetch data from the addresses in the memory device (3) requested by the processor (1) and then also fetches data from one or several addresses in the memory device (3) not requested by the processor (1). The computer system includes a circuit called the stream-detection circuit (5), connected to interact with a cache (2,4) such that the stream-detection circuit (5) detects the addresses which the processor (1) requests in the cache (2,4) and registers whether the addresses requested already existed in cache (2,4) . The stream-detection circuit (5) is arranged such that it is made to detect one or several sequential series of addresses requested by the processor (1) in the cache (2,4).

Abstract: A computer system which includes a processor having an instruction set capable of "delaying" block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps which exploits the characteristics of the instruction set and architecture of the processor in order to increase efficiency and throughput of the computer system is provided. Hence by interleaving the block-store instruction of the previous data block with the block-load instruction of the next data block, the entire block transfer process can streamlined.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: The present invention provides a mass storage system suitable for incorporation in a video-on-demand server that is capable of detecting and correct errors without a substantial increase in processor capacity or memory buffer size, and without any increase in disk input/output (I/O) bandwidth. The mass storage system includes a server controller, a cluster of data disk drives and a parity drive associated with the cluster of data disk drives. The controller provides video data streams to a number of viewers. Data is stored as contiguous data strips in the cluster of data drives. Each data strip includes a plurality of contiguous data slices logically distributed across the cluster of data drives. A plurality of parity slices, each parity slice corresponding to each data strip, is stored in the parity drive. When the failure of one of the data drives is detected, the parity drive is read in place of the failed drive.

Abstract: A substrate, an alignment plate, a heat sink, a back plate, a plurality of spacers, and a plurality of nuts are used to removably package one or more semiconductor package into a single module. The semiconductor dies are packaged with tape automated bonding (TAB) packages having land grid array (LGA) outer lead bumps. The substrate comprises a number of land patterns, a number of alignment cavities, and a number of join cavities. The alignment plate is fabricated with a number of alignment pins, a number of housing cavities, and a number of join cavities. The heat sink is fabricated with a number of stems and a number of join cavities. The back plate is fabricated with a number of extrusions having threaded ends. The spacers are fabricated with ranged openings at both ends, and each spacer is loaded with a number of spring washers. The nuts are fabricated with stepped heads.

Abstract: A computer graphics system includes a texel value generator capably of generating texel values using a minimal amount of computationally intensive divisions while maintaining a selectable texel accuracy criteria along a scan line. This is accomplished by adaptively selecting divisional points which delineate the scan line segments along each scan line such that the divisional points are as widely spaced as possible without exceeding the selected texel accuracy criteria. Having selected the texel accuracy criteria, such as a texel error bound optimally spaced, divisional points along the scan lines are selected as a function of the selected accuracy criteria. In general, since texture gradients are not evenly distributed over the surface of a given object and texture variations are present between different objects of the image, it is advantageous to adaptively select division points one at a time, skipping as many pixels in between divisional points as the local texture gradient will allow.

Abstract: The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe.

Abstract: A portable PCMCIA interface for a host computer having a system bus. In one embodiment, the host computer is a SPARC based computer having an SBus and running the UNIX operating system. The PCMCIA interface provides a user application with access to a PCMCIA card. In this embodiment, the PCMCIA interface includes software and hardware components. The software component includes a hardware-independent portion and a hardware-dependent portion. By implementing the software in a suitable high level language such as "C", the software can be easily ported to other hardware platforms by merely adapting the hardware-dependent portion. The hardware component includes an ASIC coupled between the system bus and a couple of PCMCIA sockets. In some embodiments, the hardware also includes a 5 volt to 12 volt DC--DC converter between the system bus and the PCMCIA sockets.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A method is disclosed for a method to dynamically link a new program image and related library programs into an executable application program image. The method provides for producing a linked list of the required programs by giving the linker an argument representing the designated program image and a naming context which contains data on the associated library programs which are to be linked together. The linker finds all of the required programs, and links them together. The parent maps the program images into the designated addresses thereby completing the linking of the executable application program. In finding the required programs, the linker first checks the image cache to see if the new program and its related library programs is already linked and cached because it was executed before.