Patents Represented by Attorney, Agent or Law Firm Karin L. Williams, Esq.
  • Patent number: 6724044
    Abstract: A MOSFET device design is provided that effectively addresses the problems arising from the parasitic bipolar transistor that is intrinsic to the device. The MOSFET device comprises: (a) a body region; (b) a plurality of body contact regions; (c) a plurality of source regions; (d) a plurality of drain regions; and (d) a gate region. In plan view, the source regions and the drain regions are arranged in orthogonal rows and columns, and at least a portion of the body contact regions are bordered by four of the source and drain regions, preferably two source regions and two drain regions.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: April 20, 2004
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6717346
    Abstract: An additional phosphor-excitation mechanism improves the light output of a visible-light emitting phosphor. One excitation mechanism indirectly excites the visible-light emitting phosphor by first striking a non-visible-light emitting particle (such as an ultra-violet-emitting phosphor) with an electron beam, which then emits non-visible radiation that strikes a visible-light emitting phosphor. The non-visible-light emitting particles can be disposed behind and/or adjacent to die visible-light emitting phosphors. A second mechanism directly excites the visible-light emitting phosphor by directly striking the visible-light emitting phosphor with an electron beam. Thus, the same visible-light emitting phosphor is activated by the first indirect mechanism as well as the second direct mechanism.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: April 6, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: John Friedrich Breuninger
  • Patent number: 6713352
    Abstract: A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: March 30, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6713351
    Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: March 30, 2004
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6710414
    Abstract: A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or “programmed” by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad mask are required for each new device. Wafers may also be manufactured and stored at an inventory location prior to contact or metal mask, significantly reducing the time required to manufacture new devices. It is also be possible to qualify a family of devices made using this approach without qualifying each device. In addition, the location of the source or the source and gate bonding pads may be easily moved for assembly in a new package or for a new application.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: March 23, 2004
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6711132
    Abstract: A method and apparatus is provided for use in providing real-time, packet-switched service to an end-user over a cable data network. The method begins by transmitting over the cable data network a scheduled grant to an end-user gateway in accordance with an unsolicited grant service protocol. The grant authorizes the end-user gateway to transmit a data packet to a cable modem termination system (CMTS) located in the cable data network. Next, an adjustment is made to the time at which subsequent grants are transmitted. The adjustment, which is based on a response of the end-user gateway, is performed to reduce delay between a time when a subsequent data packet is generated and receipt of the subsequent grant.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: March 23, 2004
    Assignee: General Instrument Corporation
    Inventor: David Beryl Lazarus
  • Patent number: 6707127
    Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: March 16, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Max Chen, Koon Chong So, Yan Man Tsui
  • Patent number: 6704493
    Abstract: A system and method are disclosed that accepts different types of signals from multiple sources and routes the signals to the appropriate devices for conversion or other processing so that each signal is in a common or desired format, such as the MPEG standard. The individual signal streams are packetized so that each signal stream carries identifying information associated with it originating signal source and then multiplexed onto a single digital transport stream for storage. Such a system allows overlapping signals of different types from multiple sources to be processed and stored in a single storage device. Each of the signals can then be subsequently retrieved for playback or display.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: March 9, 2004
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Ian Charles Matthews, David Alan Desch
  • Patent number: 6700875
    Abstract: In a system, device, and method for selecting a channel from among a plurality of channels, a number of available channels are selected for testing. A channel quality measurement is made for each of the number of available channels. The channel having the best channel quality measurement is then selected. To make the channel quality measurements, a primary station selects a channel to be tested and also selects a secondary station with which to perform the test. The primary station transmits a control frame to the selected secondary station, including a channel identifier identifying the selected channel. Upon receiving the control frame, the selected secondary station adjusts its transmitter to the selected channel based on the channel identifier in the control frame, and transmits a reference signal on the selected channel. Meanwhile, the primary station adjusts its receiver to the selected channel and receives the reference signal from the selected secondary station.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: March 2, 2004
    Assignee: Motorola, Inc.
    Inventors: Stephen Schroeder, Keith M. Conger, Richard Wade, Michael Jaimie Cooper
  • Patent number: 6696776
    Abstract: A coupler for coupling a projection lens to a cathode ray tube consists of a metallic plate having a first side and a second side, the first side for mounting to the faceplate of the cathode ray tube in a fluid tight relationship and the second side for mounting to a lens plate. The metallic plate is covered with a non-reflective coating and has at least one through hole for mounting to CRT rails. A plurality of ribbs protrude from the second side of the metallic plate from at least one of the at least one through holes and the ribbs surround the through hole. Upon mounting of a fastening device in the at least one through hole, the fastening device comes into contact with a top surface of the ribbs and the non-reflective coating is removed from the ribbs, thereby forming a ground connection for the coupler.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: February 24, 2004
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: John J. Florek
  • Patent number: 6689662
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: February 10, 2004
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6687486
    Abstract: A method and apparatus to configure, provision and control a set-top terminal using a wireless web appliance is provided where a wireless communications path is established between the wireless web appliance and the set-top terminal. The set-top terminal is arranged to communicate with a headend controller over a bi-directional communication link having both upstream and downstream communication paths. A configuration change is implemented in response to an unsolicited message that is generated by the set-top terminal and received by the headend controller over the upstream communications path. The configuration change is implemented at the headend, or at the set-top terminal by downloading configuration data from the headend controller over the downstream communication path. The set-top terminal transmits the unsolicited message in response to a control signal generated by the wireless web appliance that is received over the wireless communications path.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 3, 2004
    Assignee: General Instrument Corporation
    Inventor: Richard Stephen Grzeczkowski
  • Patent number: 6674124
    Abstract: A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: January 6, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6660571
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: December 9, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6658231
    Abstract: A receiver is provided for an information system that provides selected information to individual users. A high speed digital program signal is broadcast and contains program data that begins at a reference time and is repeated at set intervals. An index signal that contains the receiver's identifier associated with the reference time and interval information is also broadcast. The receiver monitors the index signal for its identifier. When the receiver detects its identifier, the receiver downloads the time and tuning information. The receiver then uses the time and tuning information to receive, download, and store the user's selected program. In some embodiments a transceiver replaces the receiver to allow the user to make remote program requests.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: December 2, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Takashi Nakatsuyama
  • Patent number: 6657255
    Abstract: A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, William John Nelson, John E. Amato
  • Patent number: 6657256
    Abstract: A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6656797
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer. A second doped layer is formed in the same manner as the first doped layer. The second doped layer is located vertically below the first doped layer.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6648906
    Abstract: A method and apparatus is provided for heating or cooling at least a selected portion of a patient's body. The method begins by inserting a catheter through the urethra and into the bladder of the patient. A heated or chilled fluid is conducted through a supply lumen of the catheter and into the bladder. The fluid is evacuated from the bladder through a return lumen of the catheter. Finally, a quantity of urine is monitored which flows out of the bladder and through the return lumen of the catheter. The rate of fluid flowing through the supply lumen of the catheter may be adjusted in a manner that is based at least in part on the monitored quantity of urine flowing out of the bladder.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: November 18, 2003
    Assignee: Innercool Therapies, Inc.
    Inventors: Juan C. Lasheras, Steven A. Yon, Michael Magers
  • Patent number: 6642734
    Abstract: When performing supply and measurement of various signals on n=8 semiconductor IC devices under test DUT1-DUT8 using m=3 substrates 10-30, reference voltages of the devices under test DUT1-DUT3 are input to the substrate 10, reference voltages of the devices under test DUT4-DUT6 are input to the substrate 20, and reference voltages of the devices under test DUT7 and 8 are input to the substrate 30. The reference voltages input to each substrate 10-30 are averaged. The mean voltages made in each substrate are further connected to each other, and a reference voltage is made using three substrates 10-30. The reference voltage is used as a reference voltage for voltage generating circuits 11-31. The reference voltage having no variation among each substrate is set even if the number of semiconductor IC devices under test is increased and the whole equipment becomes large.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: November 4, 2003
    Assignee: Hitachi Electronics Engineering Co., Ltd.
    Inventors: Shinichi Tsuyuki, Toshiaki Ogura