Abstract: A non-invasive system and process for projecting sensory data onto the human neural cortex is provided. The system includes a primary transducer array and a secondary transducer array. The primary transducer array acts as a coherent signal source, and the secondary transducer array acts as a controllable diffraction pattern that focuses energy onto the neural cortex in a desired pattern. In addition, the pattern of energy is constructed such that each portion projected into the neural cortex may be individually pulsed at low frequency. This low frequency pulsing is formed by controlling the phase differences between the emitted energy of the elements of primary and secondary transducer arrays.

Abstract: A trench DMOS transistor cell is provided, which is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.

Abstract: A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: A lightweight cathode ray tube is formed by reducing a cross-sectional area on the apeture grill tapes in the aperture grill. One exemplary embodiment of the reduced cross-sectional area aperture grill tape includes a central longitudinal channel in a side of the aperture grill tape that faces away from the screen. The reduction in cross-sectional area reduces a linear density of the tape thereby decreasing the tension required by the frame. As each of the aperture grill tapes includes this central longitudinal channel, the weight of the overall aperture grill is significantly reduced and the aperture grill frame weight is reduced due to the lower aperture grill tension. A method for producing the reduced cross-sectional area aperture grill tape is possible without significantly increasing the cost of manufacturing the aperture grill tape.

Abstract: The use of an intravascular cooling element to induce hypothermia in connection with a medical procedure. According to a first aspect of the present, invention, a coronary bypass procedure is conducted in which a patient's blood is oxygenated with the patient's lungs and in which blood is circulated using the patient's heart or using an intracorporeal pump. The procedure preferably comprises: (a) positioning a heat transfer element in a blood vessel of a patient; (b) cooling the body of the patient to less than 35° C., more preferably 32±° C., using the heat transfer element; and (c) forming a fluid communicating graft between an arterial blood supply and the coronary artery. The body of the patient is preferably heated to about 37° C. using the heat transfer element subsequent to the step of forming the fluid communicating graft.

Abstract: A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p-n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions.

Abstract: A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, each segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type region. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions, and a plurality of first conductivity source regions are within upper portions of polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

Abstract: A trench DMOS transistor cell includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The source region includes a first layer and a second layer disposed over the first layer. The first layer has a lower dopant concentration of the first conductivity type relative to the dopant concentration of the second layer.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A hybrid semiconductor device comprises four identical semiconductor diode chips each having top and bottom surfaces. Each chip is mounted on a respective mounting pad all of which lie in a common plane and, for ease of assembly, the four chips are mounted in identical top to bottom orientation, e.g., bottom surface down and electrically connected to the mounting pads. In one embodiment, the mounting pads for the chips and terminals for the device are integral with leads of a single (“component”) lead frame and various electrical connectors for the chips comprise bonding wires or stamped metal jumpers added to the workpiece after the chips are mounted on the lead frame. The metal jumpers can be provided on a separate “jumper” lead frame used in cooperation with the component lead frame, or the jumpers can comprise portions of leads of the single component lead frame. Printed circuit boards embodiments are also disclosed.

Abstract: A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.

Abstract: A method and apparatus for displaying a video signal is described. A video signal is received representing an image having a first aspect ratio, with the image having a top and bottom edge. An edge modification signal is generated. The image is displayed on a display having a second aspect ratio with the top and bottom edge modified in accordance with the edge modification signal. Accordingly, burn lines are minimized through use of the edge modification signal to reduce brightness levels at the top and bottom edge of the image.

Abstract: A housing for electronic circuits designed, illustratively, for use in cable television networks includes a specialized electrically conductive grounding clip that establishes grounding contact between an exterior surface of a first housing element and an interior surface of a second housing element, the first housing element being positionable within an opening in the second housing element such that the interior and exterior surfaces are substantially aligned. The grounding deice includes an intermediate section defining a first end and a second end and a through opening, with an arcuate spring biased grounding clip extending along the through opening. First and second integral flange sections extend from the first and second ends of the intermediate section, respectively, and are dimensioned and arranged to apply retention forces, to substantially opposing surfaces of one of the housing elements so that the ground clip is held in place without the need for a mechanical fastener or adhesive.

Abstract: A hybrid semiconductor device comprises four identical semiconductor diode chips each having top and bottom surfaces. Each chip is mounted on a respective mounting pad all of which lie in a common plane and, for ease of assembly, the four chips are mounted in identical top to bottom orientation, e.g., bottom surface down and electrically connected to the mounting pads. In one embodiment, the mounting pads for the chips and terminals for the device are integral with leads of a single (“component”) lead frame and various electrical connectors for the chips comprise bonding wires or stamped metal jumpers added to the workpiece after the chips are mounted on the lead frame. The metal jumpers can be provided on a separate “jumper” lead frame used in cooperation with the component lead frame, or the jumpers can comprise portions of leads of the single component lead frame. Printed circuit boards embodiments are also disclosed.

Abstract: An HFC return path system uses digital conversion and transport at the fiber optic node, so as to replace analog laser technology with a high-speed baseband digital technology, thereby providing immunity from the troublesome analog laser impairments, enabling longer distances to be covered, potentially avoiding the need for hub repeater hardware required in analog systems, among other benefits.

Abstract: A method and apparatus for displaying a video signal is described. A first video signal is received representing a first image having a first aspect ratio. The first image is displayed on a display having a second aspect ratio and a display area, with the first image having a smaller area than the display area forming a border area. A second video signal is received representing a second image having the second aspect ratio. A border modification signal is generated. The second image is displayed on the display with the border area modified in accordance with the border modification signal.

Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.