Abstract: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the floating point numbers divided, the unit of least precision, and the unit of least precision plus one to determine where the infinitely precise result is with respect to the digital representation of the estimated quotient. Evaluating these remainders and the initial floating point numbers and comparing their signs and magnitudes leads to a selection of one of three choices as the most accurate representation of the infinitely precise result as calculated in the inventive rounding method: the intermediate result minus the unit of least precision; the intermediate divide result; or the intermediate divide result plus the unit of least precision.

Abstract: A method and apparatus for a cache line cut through reduces the latency and memory bandwidth of a data processing system. By cutting through or forwarding a cache line to the next processing element, data that has been read from a local memory into a local cache and altered by a processing element need not be restored to the local memory before it is sent to its destination target processing element. By eliminating the write back to the local memory for direct write through to the destination, performance is increased because the bandwidth and latency are decreased. In a preferred embodiment, the processing elements may be contained within a network processor and the altered data may be a header in one network protocol which needs to be modified to another protocol before transfer of the data along the network. Transfer of the data may be to another network processor, another processing element, or to another memory.

Abstract: Applications/functions within an electronic processing device having a GPS card and antenna, such as a laptop or personal digital assistant, can be enabled only when in a specified geographic location. For each critical application/function, its accessibility is programmed to be enabled/disabled only in specified geographic regions. No additional passwords are required: access or abortion of an running program are automatic. The geographic regions can be input into the electronic processing device using GPS processing or using a graphical user interface on a map. Other methods of determining the boundaries of the appropriate geographic regions for each applications/functions are disclosed. An application/function will not be opened if the electronic device is not within the geographic region associated with the application/function.

Abstract: A conductive sash is etched around the periphery of a land grid array interconnection on a carrier for dense integrated circuit connections. If the array comprises more than one module or module chip domain, the conductive sash is also positioned between the modules. The dimensions of the sash are such that it is slightly larger than a frame of an interposer or other electrical connector which is placed upon the array. In this fashion, the interposer or other electrical connector rests upon the sash and provides protection against particulate and gaseous contamination of the array.

Abstract: An electronic processing device having GPS card and antenna, such as a laptop or personal digital assistant, can be enable only when a geographic-specific password is entered. Geographic regions are established in the electronic processing device with a user interface and priorities can be granted to the regions. The user further stores a geographic-specific password for each of the geographic regions. When the user travels and wishes to enable the electronic processing device, the GPS card and antenna receive and process the device's current location. When the user inputs a password, the electronic device determines if the password is appropriate for the current location. If not, access is denied.

Abstract: A queue, such as a first-in first-out queue, is incorporated into a processing device, such as a multithreaded pipeline processor. The queue may store the resources of more than one thread in the processing device such that the entries of one thread may be interspersed among the entries of another thread. The entries of each thread may be identified by a thread identification, a valid marker to indicate if the resources within the entry are valid, and a bank number. For a particular thread, the bank number tracks the number of times a head pointer pertaining to the first entry has passed a tail pointer. In this fashion, empty entries may be used and the resources may be efficiently allocated. In a preferred embodiment, the shared resource queue may be implemented into an in-order multithreaded pipelined processor as a queue storing resources to be dispatched for execution of instructions.

Abstract: Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit are output that determine the integer and fractional number of the high speed oscillating clock periods which occurred during one reference clock cycle. The measurements are very accurate and all cycles of the reference clock are measured. Such measurements enable various frequency control schemes over the high speed oscillating clock source.

Abstract: An occupancy alarm system can be integrated into a motor vehicle or can be portable. The occupancy alarm system may be programmed to communicate with a program within a logic unit of the on-board computer within the vehicle or a cellular telephone or other wireless logic device so that if the driver's door is open and the engine is turned off but there still is an occupant in the motor vehicle, an alarm is immediately triggered. The GPS coordinates of the motor vehicle or the cellular telephone or other wireless device may be communicated to a remote location service or a local emergency center as part of the alarm. The occupancy sensor may be mounted on the occupant or on the restraint system, and may interact with an ambient temperature sensor and an alarm, both of which may be integrated into a motor vehicle, to indicate that a dangerous condition exists for an occupant within the motor vehicle.

Abstract: An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution.

Abstract: A playback program for DVDs and CDs enables a user to customize the playback of the disk. Regions that are independent of prerecorded tracks are created and/or played back based on the content of the disk, e.g., visual content or audio content, in those regions. Thus, for instance, certain scenes or certain dialogue of the disk can be skipped over during playback because an attribute to skip or otherwise modify the output was assigned to a particular region during creation of the program. Several start-up modes can be programmed during creation of the program to indicate whether the disk will initially skip to the first region whose output is modified or playback normally until a region with an modified output is encountered. A password may be required to access the playback program.

Abstract: Multiple links to the same object are managed by storing the attributes of the object in only one place. Each directory which links to the object has an object attribute table; each table has a number of entries all capable of storing the attributes of the files linked to the directory. One of the entries in a directory linked to a file stores the attributes of that file, called the master entry; other entries in the same or other directories that also link to the same file have slave entries capable of storing the attributes but not storing the attributes in their respective object attribute table. The file need only address the master entry. The master entry may point to the other slave entries which may point back to the master or to other slave entries as determined by a pointer protocol. When the master entry is to be deallocated, another of the qualified slave entries receives the attribute information and the file is updated to reflect that a new master has been declared.

Abstract: In a multithreaded processor, a method and an apparatus to selectively disable one or more threads is disclosed. As multithreading is increasingly becoming the normative paradigm of computer architecture, there still may instances which warrant disabling a thread, such as using operating systems not coded for the specific number of threads, having defective registers/arrays peculiar to a thread, certain kinds of testing procedures. Thus a method is disclosed to test the function of each thread separately and discern if any threads have defective register/arrays. If so or for other reasons, a method and apparatus are disclosed to selectively disable access to the registers/arrays peculiar to the thread. Features of the invention allow the disablement of individual storage elements in multithreaded registers/arrays or to disable access to hardware registers or individual bits in hardware registers associated with the failed thread.

Abstract: A powerplane for use in a backplane power distribution system. The backplane includes a conductive sheet for distributing power from a power source to a load. The powerplane further includes source locations and load locations for coupling the conductive sheet to a power source and a load. The conductive sheet has resistances with appropriate spacing and dimensions so that the resistance near the source locations is greater than the resistance farther away from the source locations. Thus, current is shared more evenly between all the load locations, and the voltage difference between distant load locations and near load locations is reduced to near zero.

Abstract: In a computer windowing operating environment: a method, apparatus, and program product to select the appropriate window controller corresponding the motion of the window cursor. A user will activate a first window controller by clicking on a mouse or other input means and then may drag the window cursor/arrow some distance across the window. In accordance with features of the invention, the original position and the motion of the cursor/arrow are recorded. If the motion is inconsistent with the first controller associated with the original position of the cursor/arrow, a next controller is selected and evaluated as controlling a function consistent with the motion. The process is repeated until a controller within a threshold distance of the original position accepts the motion as being consistent with its functions. Data of the original position and the cursor/arrow motion is passed to the accepted window controller and that window controller then assumes control of the window.

Abstract: A conductive sash is etched around the periphery of a land grid array interconnection on a carrier for dense integrated circuit connections. If the array comprises more than one module or module chip domain, the conductive sash is also positioned between the modules. The dimensions of the sash are such that it is slightly larger than a frame of an interposer or other electrical connector which is placed upon the array. In this fashion, the interposer or other electrical connector rests upon the sash and provides protection against particulate and gaseous contamination of the array.

Abstract: A redundancy manager preferably in an I/O adapter has been disclosed to manage commands to peripheral devices in a computer system. These peripheral devices have multiple ports and may have a different bus associated with each port. The buses, referred to as independent pathways, moreover, need not have the same protocol. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based on load balancing considerations and any ordering semantics that must be preserved in the incoming command and any outstanding commands and associated data that have not yet executed.

Abstract: A method to improve object-oriented computer processing by reducing the incidences of object creation and garbage collection. A compiler, preferably of object-oriented language such as Java, identifies a list of objects that are fixed in value or are constant and places those fixed/constant objects in a separate class, a root class, which is loaded at run-time along with all the other classes. Upon creation of an object table, a separate object table may be created for those objects in the root class thereby immunizing the fixed entries from garbage collection and the values will not be erased from memory. Alternatively, the fixed/constant objects can be placed in an object table along with other variable objects but can be marked as active by changing the bit values in a field of the object table.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: In a simultaneous multithread processor, a flush mechanism of a shared pipeline stage is disclosed. In the preferred embodiment, the shared pipeline stage happens to be one or all of the fetch stage, the decode stage, and/or the dispatch stage and the flush mechanism flushes instructions at the dispatch stage and earlier stages. The dispatch flush mechanism detects when an instruction of a particular thread is stalled at the dispatch stage of the pipelined processor. Subsequent instructions of that thread are flushed from all pipeline stages of the processor up to and including the dispatch stage. The dispatch stage is distinguished as being the stage in which all resources necessary for the successful dispatch of the instruction to the issue queues are checked. If a resource required only by that instruction is unavailable, then a dispatch flush is performed. Flush prioritization logic is available to determine if other flush conditions, including a previous dispatch flush, exist for that particular thread.

Abstract: A method, apparatus, and a program product to protect against thread loss in a multithreaded computer processor. The processor may experience the failure of one or more threads; in accordance with the invention, a functional test can be run to determine which thread is experiencing the failure. If the thread failure results the failure of a register/array that is uniquely associated with the thread, then the invention will disable access to those register/arrays. Each thread may have its own set of register/arrays or it may be uniquely assigned to one of a plurality of storage elements in a multithreaded register/array. Using this invention, a processor may continue processing other threads and the instructions and data associated with the disabled or defective thread can be rerouted.