Abstract: An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during thread switching. Register overwrite buffers preserve thread resources in overlapping registers during the thread switching process. Thread resources are loaded into the corresponding register subsets or, when overlapping register subsets are employed, into either the corresponding register subset or the corresponding register overwrite buffer. A thread status register is utilized by a thread controller to keep track of READY/NOT-READY threads, the active thread, and whether single-thread or multithread operations are permitted. Furthermore, the registers in the register subsets include a thread identifier field to identify the corresponding thread.

Abstract: An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently.

Abstract: In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. The register/storage functional units are interrogated dynamically so that this transfer occurs only when the register/storage functional units are idle and not being used for normal instructions. Thus, a state may be transferred in whole if there are many cycles when the register/storage functional unit is idle or it may be transferred in part if there an insufficient number of no-op instructions for the entire state. A context switch unit in the processor then has appropriate registers and logic control to keep track of the state of the thread that is being “idly” transferred and then transfer the remaining registers when a register/storage functional is available or “idle.

Abstract: An electrical connection assembly for use in computer systems is disclosed. In the preferred embodiment, the computer system contains a backplane circuit card assembly for distribution of electrical signals to one or more pluggable modules. The modules are plugged into the backplane of the computer system without interrupting power to the computer system. The robust power connection is over-rated for the actual current and voltage delivered to the pluggable modules; and if any damage does occur at the point of initial contact, the connector surfaces are wiped beyond the initial contact point to the site of actual electrical contact which can occur at any place on a plurality of redundant surfaces. In this fashion, the connector assembly tolerates the arcing that occurs when the module is plugged into power grid on the backplane.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A dual current source circuit provides dual currents of the same magnitude and having coefficients of temperature compensation that are also equal but opposite. The core of the circuit is a degenerated differential pair of bipolar junction transistors wherein the base of a first transistor of the pair is connected to a bandgap voltage reference. The base of the second transistor of the pair is connected to a PTAT current source having only one of a positive or a negative coefficient of temperature compensation and a resistor which generates a voltage difference between the bases of the two transistors. This voltage difference generates dual currents, each having equal but opposite coefficients of temperature compensation. A temperature independent stable tail current is provided to the transistors and can be generated by summing the current output of a negative PTAT current source and a positive PTAT current source.

Abstract: A semiconductor-on-insulator integrated circuit with buried patterned layers as electrical conductors for discrete device functions, thermal conductors, and/or decoupling capacitors.

Abstract: In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel.

Abstract: A magnetic recording disk of a disk drive apparatus is constructed having a radially sloped surface, so that the outer area of the disk is thinner than the inner area. The radially downward slope of the disk surface has the effect of increasing the crown of the disk head, this effect being greatest closest to the disk axis and decreasing as the head moves toward the outer diameter. A head landing zone is preferably located at the inner part of the disk surface, where the crown is greatest, reducing stiction during disk start-up. Furthermore, the gradual reduction in crown as the head moves radially outward compensates for the increasing velocity of the head relative to the disk surface, achieving a more uniform flying height of the disk head.

Abstract: A magnetoresistive (MR) reproduction element is positioned during data recording, data reproduction, and formatting so that its total range of movement is 3/2 times a range of movement (microjogging) from the location of the reproduction element in data recording to the location of the reproduction element in data reproduction. The total range of movement is centered within a range where the detection of positional error of the reproduction element changes linearly. Therefore, in the respective data recording, data reproduction and formatting processes, microjogging is performed and the detection of positional error changes linearly for each of an off-track OF.sub.W in data recording, an off-track OF.sub.R in data reproduction, and an off-track OF.sub.F in formatting. Accordingly, the characteristics of the MR reproduction element can be effectively used to a maximum degree and information can be reproduced without being undetected or erroneously detected.

Abstract: A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

Abstract: A networked computer system and method of communicating classify request packets into multiple classes, with one class devoted to non-propagable requests that may be handled locally by destination nodes in the computer system. The multiple classes of requests are separately handled in the networked computer system such that an inability of a node to handle a request in another class does not hinder the ability of the node to process non-propagable requests, thereby avoiding deadlocks in the computer system.

Abstract: The invention is a method to mark hypertext links in an image map that have been traversed. The invention actually modifies the image map of the links by inserting a marker or changing the color associated with the coordinates of a particular image link on the image map. The history files of links that have been traversed are first checked to determine if the image has changed or is otherwise out of date. The image map or a copy of the image map is then modified and displayed.

Abstract: A cleavable epoxy resin composition suitable for encapsulating electronic chips and a method for making the composition comprises the cured reaction product of a diepoxide; a cyclic dicarboxylic anhydride curing agent mixture; a 1,3-diaza compound having two nitrogen atoms present with one nitrogen atom doubly bonded to the central carbon and singly bonded to one other carbon, and the other nitrogen atom singly bonded to the central carbon and singly bonded to another carbon and singly bonded to a hydrogen. The 1,3-diaza compound serves either as the sole catalyst or in combination with a tertiary amine catalyst different from the diaza compound. The composition may include an optional hydroxy functional compound capable of reacting with the cyclic anhydrides to form a half ester thereby initiating the reaction between the diepoxide and the cyclic dicarboxylic anhydride curing agent. The resin can be used for the encapsulation of electronic parts, but can be removed by a solvent.

Abstract: A sorting algorithm is applied to an array data structure to arrange array elements according to the predicted frequency by which those array elements are likely to be modified. Higher modification frequency array elements are arranged proximate the end of the array to minimize the number of array elements that will typically need to be updated in response to modification of these array elements, reserving the modifications that require more array elements to be updated to those array elements that have a lower likelihood of modification. A sorting algorithm suitable for use in memory compression arranges blocks for a given page in reverse order since data located proximate the beginning of a page has a higher probability of being modified than the data proximate the end of the page.

Abstract: A redundant disk storage system having data stored on one disk and identical data on second disk, wherein the data stored on the second disk is in a different radial location determined by an offset. The offset could be such that the data on the first disk is stored near the inner circumference and the identical data is stored on the second disk near the outer circumference. Moreover, a RAM associated with each disk drive which stores the address and offset eliminates a RAM in the main disk controller.