Abstract: A method of plasma etching a patterned tantalum nitride layer, which provides an advantageous etch rate and good profile control. The method employs a plasma source gas comprising a primary etchant to provide a reasonable tantalum etch rate, and a secondary etchant/profile-control additive to improve the etched feature profile. The primary etchant is either a fluorine-comprising or an inorganic chlorine-comprising gas. Where a fluorine-comprising gas is the primary etchant, the profile-control additive is a chlorine-comprising gas. Where the chlorine-comprising gas is the primary etchant, the profile-control additive is an inorganic bromine-comprising gas. By changing the ratio of the primary etchant to the profile-control additive, the etch rate and etch profile of the tantalum nitride can be controlled. For best results, the plasma is preferably a high density plasma (minimum electron density of 1011e−/cm3), and a bias power is applied to the semiconductor substrate to increase the etching anisotropy.

Abstract: We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. We have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at the bottom of a high aspect ratio contact via and on the walls of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. An increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, including but not limited to applicants' preferred technique, an inductively coupled RF ion metal plasma.

Abstract: The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i.e., the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 &mgr;m and having a platinum profile equal to or greater than about 85°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising chlorine, argon and a gas selected from the group consisting of BCl3, HBr, and mixtures thereof. A semiconductor device having a substrate and a plurality of platinum electrodes supported by the substrate. The platinum electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 &mgr;m and a platinum profile equal to or greater than about 85°.

Abstract: This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched.

Abstract: We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325° C., it is possible to obtain an ultra low resistivity which is lower than that previously published in the literature. In addition, it is possible deposit a TaxNy film having an ultra low resistivity by depositing the TaxNy film upon a substrate at a temperature of at least 275° C., wherein x is 1 and y ranges from about 0.05 to about 0.18. These films having an ultra low resistivity are obtained at temperatures far below the previously published temperatures for obtaining higher resistivity films. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining optimum film properties.

Abstract: A physical vapor deposition apparatus is provided with at least one workpiece processing chamber and a programmable control device for controlling process variables within the processing chamber. The control device is programmed to vary the power to an aluminum sputtering target during deposition of aluminum layers. By controlling the applied power, the rate of deposition of the aluminum is varied in a manner which reduces or avoids the creation of voids during the filling of high aspect ratio features.

Abstract: The present invention pertains to a semiconductor device microstructure, and to a method of forming that microstructure, which reduces or prevents junction spiking and to a method of forming that microstructure. In particular, a semiconductor contact microstructure comprises a feature which includes a silicon base and at least one sidewall extending upward from the silicon base. The sidewall includes a silicon portion in contact with the silicon base, where the height of the silicon portion of the sidewall above the silicon base is typically less than about 0.5 &mgr;m. The sidewall also includes at least one portion which comprises a first dielectric material which is in contact with (and typically extends upward from) the silicon portion of the sidewall. Overlying at least the silicon portion of the sidewall is a layer of a second dielectric material, preferably silicon oxide.

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Abstract: In an embodiment of the present invention, a method is provided of patterning PZT layers or BST layers. For example, a PZT layer or a BST layer is plasma etched through a high-temperature-compatible mask such as a titanium nitride (TiN) mask, using a plasma feed gas comprising as a primary etchant boron trichloride (BCl3) or silicon tetrachloride (SiCi4). Although BCl3 or SiCl4 may be used alone as the etchant plasma source gas, it is typically used in combination with an essentially inert gas. Preferably the essentially inert gas is argon. Other potential essentially inert gases which may be used include xenon, krypton, and helium. In some instances O2 or N2, or Cl2, or a combination thereof may be added to the primary etchant to increase the etch rate of PZT or BST relative to adjacent materials, such as the high-temperature-compatible masking material. A TiN masking material can easily be removed without damaging underlying oxides.

Abstract: The present disclosure pertains to the discovery that TiN films having a thickness of greater than about 400 Å and, particularly greater than 1000 Å, and a resistivity of less than about 175 &mgr;&OHgr;cm, can be produced by a CVD technique in which a series of TiN layers are deposited to form a desired TiN film thickness. Each layer is deposited employing a CVD deposition/treatment step. During a treatment step, residual halogen (typically chlorine) was removed from the CVD deposited film. Specifically, a TiN film having a thickness of greater than about 400 Å was prepared by a multi deposition/treatment step process where individual TiN layers having a thickness of less than 400 Å were produced in series to provide a finished TiN layer having a combined desired thickness. Each individual TiN layer was CVD deposited and then treated by exposing the TiN surface to ammonia in an annealing step carried out in an ammonia ambient.

Abstract: The present disclosure pertains to particular Ti/TiN/TiNx barrier/wetting layer structures which enable the warm aluminum filling of high aspect vias while providing an aluminum fill exhibiting a high degree of aluminum <111> crystal orientation. It has been discovered that an improved Ti/TiN/TiNx barrier layer deposited using IMP techniques can be obtained by increasing the thickness of the first layer of Ti to range from greater than about 100 Å to about 500 Å (the feature geometry controls the upper thickness limit); by decreasing the thickness of the TiN second layer to range from greater than about 100 Å to less than about 800 Å (preferably less than about 600 Å); and, by controlling the application of the TiNx third layer to provide a Ti content ranging from about 50 atomic percent titanium (stoichiometric) to about 100 atomic percent titanium.

Abstract: A method and assembly for recovering a metal from by-products produced from etching a metal (e.g., platinum, iridium, aluminum, etc.) in a plasma processing chamber. The method includes recovering from the plasma processing chamber a deposit of the by-products containing the metal. The deposit is dissolved in an acid, and the metal is recovered from the acid by inserting a working electrode, a reference electrode, and a counter electrode into the acid and applying a difference in potential between the working and reference electrodes to cause current to flow through the working and counter electrodes and the metal to be removed from the liquid and deposit on the working electrode. The metal is removed from the working electrode to recover the metal.

Abstract: In accordance with the present invention, during a polysilicon etch back, a controlled amount of oxygen (O2) is added to the plasma generation feed gases, to reduce pitting of the etched back polysilicon surface. The plasma etchant is generated from a plasma source gas comprising: (i) at least one fluorine-containing gas, and (ii) oxygen. The invention may be practiced in any of a number of apparatus adapted to expose polysilicon to a plasma etchant. One preferred apparatus is a decoupled plasma source (DPS™, Applied Materials, Santa Clara, Calif.) etching system. Another preferred apparatus is a magnetically enhanced plasma (MXP™, Applied Materials, Santa Clara, Calif.) etching system.

Abstract: The present disclosure provides a method for etching metal-comprising layers within a semiconductor structure using an inorganic dielectric hard masking layer. A typical stacked metal layer structure for practicing the method of the invention includes, from top to bottom, an inorganic dielectric hard masking layer, an anti-reflection (ARC) layer, a conductive layer, a diffusion barrier layer, and a dielectric layer, all deposited on a surface of a silicon substrate. When the inorganic dielectric hard masking layer is pattern etched, using an overlying photoresist mask, residual photoresist is removed prior to subsequent steps in which underlying metal-comprising layers are etched. The metal-comprising layers are then etched using a chlorine-based plasma, using the inorganic dielectric layer as a hard mask. The method of the invention provides good etch profile control without undesirable polymeric contamination.

Abstract: A method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. Using a contact via as an example of a high aspect ratio feature, we have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at both the bottom of the via and on the wall of the via . This increase is achieved by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. For features having a 0.25 &mgr;m or smaller feature size, an aspect ratio of about 3:1 requires that about 50% or more of the copper species be ions at the time of deposition on the substrate.

Abstract: We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having <111> texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.

Abstract: The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases.

Abstract: The present disclosure pertains to an integrated post-etch treatment method which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. An overlying photoresist layer and anti-reflection layer are removed during the performance of the post-etch treatment method. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed.

Abstract: The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O2).