Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

Abstract: A typical domino logic circuit has a foot device, which is the n-type evaluate transistor coupled between the n-type logic circuitry receiving the data inputs and the ground potential. This AND function provides an opportunity to move full domino AND blocks fed by full domino books of any type to the clock input of the source book. This makes the source book act like a pseudo-clocked book with a reset that must propagate from the AND block moved to its clock input. If the AND block were on the critical path, a complete stage of logic can be removed.

Abstract: As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.

Abstract: The present invention is a system, method, and computer readable medium for representing program event trace information in a way which is very compact and efficient, and yet supports a wide variety of queries regarding system performance. The tracing and reduction of the present invention may be dynamic, in which case information is obtained and added to the trace representation in real-time. Alternately, the tracing and reduction may be static, in which case a trace text file or binary file is obtained from a trace buffer, and the reduction takes place using the trace file as input. The trace information, whether obtained statically or dynamically, is represented as a tree of events. The present invention may be used to present many types of trace information in a compact manner which supports performance queries.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: During the recording of events occurring within the operation of a data processing system, a user-selected metric of interest is recorded along with the trace data for each recorded event. The metric of interest is a monotonically increasing variable that provides a non-time relationship between the recorded events. This relationship may be time or non-time based.

Abstract: A cache replacement algorithm improves upon a least recently used algorithm by differentiating between cache lines that have been written with those that have not been written. The replacement algorithm attempts to replace cache lines that have been previously written back to memory, and if there are no written cache lines available, then the algorithm attempts to replace cache lines that are currently on page and on bank.

Abstract: Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of these instructions within the multiple groups. The renaming mechanism includes a rename table allocated for each dispatched group. A delay register is implemented between a portion of the dispatch queue dispatching a second one of the groups of instructions and a second one of the rename tables.

Abstract: Carbon nanotubes are aligned within a host phase of a material that has molecules that will align under a certain influence. When the host molecules become aligned, they cause the carbon nanotube fibers to also become aligned in the same direction. The film of aligned carbon nanotubes is then cured into a permanent phase, which can then be polished to produce a thin film of commonly aligned carbon nanotube fibers for use within a field emission device.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing treatment of a substrate and then depositing the film. The treatment step creates nucleation and growth sites on the substrate for the film deposition process and promotes election emission of the deposited film. With this process, a patterned emission can be achieved without post-deposition processing of the film. A field emitter device can be manufactured with such a film.

Abstract: The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (“PLL”) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period.

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. Then when new load or store instructions are issued, the new load or store instructions are compared to entries within the load and store reorder queues to detect out of order problems.

Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.

Abstract: A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.

Abstract: An apparatus for testing semiconductor devices including probe tips for contacting input/output pads on the device attached to a probe membrane fixed to a package using a layer of elastomeric material. The elastomeric material and use of compliant bump probe tips effect a global planarization for improved electrical contact between the probe assembly and the input/output contacts on the device under test.

Abstract: When building an image for a JavaOS client, a date/time stamp is inserted into the symbolic image produced. When a trace program is initiated against this image, the same Build Identifier is inserted into the produced trace data. A comparison is made between the Build Identifiers to ensure that the trace file is analyzed using the correct symbolic image.

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

Abstract: A redesigning of dynamic logic circuitry inputs into a process implemented in a computer the dynamic logic circuitry to be redesigned as a set of boolean equations. Along a path through the logic circuitry, the logic circuitry is converted into AND and OR books, or blocks of circuitry. Then various portions of these books are compared to a library of AND/OR and OR/AND books. A list of these possible substitutions from the comparison step is produced. From the list, a selection process selects those substitutions providing a best cost benefit.