Abstract: A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.

Abstract: Fixed point instructions ADD, ROTATE, COMPARE-TO-ZERO, AND, OR and COUNT-LEADING-ZEROS are each performable in one circuit or macro. Such fixed point instructions may be implemented within an execution unit in a microprocessor, microcontroller, or digital signal processor.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing etching of a substrate and then depositing the film. The etching step creates nucleation sites on the substrate for the film deposition process. With this process patterning of the emitting film is avoided. A field emitter device can be manufactured with such a film. A field emission device results where the cathode has a continuous film that has not been subjected to etching, and thus has superior emission properties. A pixel in the cathode includes the emitting film deposited directly on the substrate with the conductor deposited on one or more sides of the emitter film. In one embodiment the emitter is in a window formed in the conductor layer.

Abstract: A processor performance evaluation system and method provides a method of model decomposition and trace attribution by first decomposing a full pipelined model of the entire system into a main model and one or more additional sub-models, such that it is possible to build fast trace-driven non-pipelined simulation models for the sub-models to compute specific metrics or values, which would be required during full-model, pipeline simulation. The main model is a fully pipelined model of the entire system; however, the simulation work required for the sub-units characterized by the sub-models is not coded into the simulation engine. Instead, the necessary values are provided from encoded fields within the input trace.

Abstract: The present invention is a system, method, and computer readable medium for representing program event trace information in a way which is very compact and efficient, and yet supports a wide variety of queries regarding system performance. The tracing and reduction of the present invention may be dynamic, in which case information is obtained and added to the trace representation in real-time. Alternately, the tracing and reduction may be static, in which case a trace text file or binary file is obtained from a trace buffer, and the reduction takes place using the trace file as input. The trace information, whether obtained statically or dynamically, is represented as a tree of events. The present invention may be used to present many types of trace information in a compact manner which supports performance queries.

Abstract: A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal.

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

Abstract: An apparatus for testing semiconductor devices including probe tips for contacting input/output pads on the device attached to a probe membrane fixed to a package using a layer of elastomeric material. The elastomeric material and use of compliant bump probe tips effect a global planarization for improved electrical contact between the probe assembly and the input/output contacts on the device under test.

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

Abstract: A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses.

Abstract: A field emission lamp, of either a diode or triode structure has a packaging whereby electrical access to the various electrodes of the lamp is provided through the rear or underside of the field emission device so that the individual lamps can be placed in close proximity to each other.

Abstract: A cache memory comprising a plurality of memory locations and a multiplexer tree for accessing selected memory locations and reordering the data retrieved from the selected memory locations prior to outputting the data to the processor. The multiplexer tree is controlled by an adder/decoder circuit which generates an effective address from two address operands and causes the multiplexer tree to perform the steps of accessing the data and re-ordering the data at least partially in parallel, thereby reducing memory latency.

Abstract: Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge sharing noise. This noise ultimately arises from leakage and stray capacitances at the nodes between MOS devices in each stack which the common node must supply. The noise is eliminated by employing MOS devices associated with the MOS devices in the stacks to couple the nodes between stack MOS devices to a supply voltage until their associated stack device changes logic state. On the changing state of the associated stack device, the node charging MOS device turns off, allowing the nodes to assume states defined by the input signals to the dynamic logic circuit.

Abstract: Within a superscalar processor implementing parallel processing of instructions, machine context synchronization operations, which may alter the context or state of the processor, are allowed to be executed in parallel with non-interruptible instructions under certain conditions. Such a condition includes the absence of a side effect of the change of context resulting from the machine context synchronization operations on the non-interruptible instructions.

Abstract: A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.

Abstract: Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.

Abstract: The present invention provides for a field emission device including an anode assembly and a cathode assembly, wherein the cathode assembly further includes a substrate, a plurality of electrically conducting strips deposited on the substrate, and a continuous layer of diamond material deposited over the plurality of electrically conducting strips and portions of the substrate exposed between the plurality of electrically conducting strips. The field emission device may further include a grid assembly including a perforated silicon substrate, a first dielectric layer deposited on the silicon substrate, and a first conducting layer deposited on the first dielectric layer, wherein the first dielectric layer and the first conducting layer have perforations coinciding with perforations of the silicon substrate.

Abstract: Performance monitoring capabilities are expanded to an entire data processing system so that performance analyses can be made for operations occurring within the entire data processing system and not merely within the processor or any other device containing the performance monitor. Therefore, there is a provision for communicating performance monitor-related signals between the various performance monitors within the various devices and processor within a data processing system.

Abstract: In a superscalar data processing system, instructions, which are dependent upon each other, are paired for dispatch to a plurality of execution units. Pairing results in instructions being paired that may not necessarily be located at contiguous addresses. Pairing may be performed by comparing general purpose register source pointers and general purpose register target pointers of the various instructions. Pairing may also be accomplished by comparing target identification numbers of source operands with target identification numbers of target instructions.

Abstract: In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.