Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.

Abstract: A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.

Abstract: A method of managing network traffic within a wireless network (100) comprises identifying a plurality of base stations (111, 121, 131) within the wireless network, categorizing each one of the plurality of base stations according to its type, setting a load balancing parameter (?) for each one of the plurality of base stations according to its type, and, for a handover event involving a handover from a first one of the plurality of base stations to a second one of the plurality of base stations, selecting the second one of the plurality of base stations according to a process that takes into account the load balancing parameters of both the first one of the plurality of base stations and the second one of the plurality of base stations.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: A structure that may be used in substrate solder bumping comprises a substrate (110), a solder resist layer (120) disposed over the substrate, a plurality of solder resist openings (121) in a surface (122) of the solder resist layer, a conformal barrier layer (130) having a first portion (131) over the surface of the solder resist layer and a second portion (132) in the solder resist openings, a mask layer (140) over the first portion of the conformal barrier layer, and a solder material (150) in the solder resist openings over the metal layer. The conformal barrier layer acts as a barrier against interaction between the solder resist layer and the mask layer during solder reflow.

Abstract: A method of forming a pattern (700) on a work piece (1260) includes placing a pattern mask (1210) over the work piece, placing an aperture (100, 500, 600, 1220) over the pattern mask, and placing the work piece in a beam of electromagnetic radiation (1240). The aperture includes three adjacent sections. A first section (310) has a first side (311), a second side (312), and a first length (313). A second section (320) has a third side (321) adjacent to the second side, a fourth side (322), a second length (323), and a first width (324). A third section (330) has a fifth side (331) adjacent to the fourth side, a sixth side (332), and a third length (333). The first and third lengths are substantially equal. The first and third sections are complementary shapes, as defined herein.

Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Abstract: A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a portion of the outer surface of the carbon nanotube. The carbon coating may be applied to the carbon nanotube by providing a nitrile-containing polymer, coating the carbon nanotube with the nitrile-containing polymer, and pyrolyzing the nitrile-containing polymer in order to form the carbon coating on the carbon nanotube. The carbon nanotube may further be coated with a low contact resistance layer (130) exterior to the carbon coating and a metal layer (140) exterior to the low contact resistance layer.

Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.

Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Abstract: An integrated circuit package comprises a package substrate (210, 410), an electrically insulating material (220, 420) adjacent to the package substrate, and a mark (230, 420) on the electrically insulating material. The mark is such that a visual contrast between the mark and the electrically insulating material is maximized when the mark and the electrically insulating material are exposed to coaxial illumination. In one embodiment the electrically insulating material over the package substrate has a first surface roughness and a mark on the solder resist material has a second surface roughness that is no more than approximately twenty times greater than the first surface roughness.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract: Decoupling capacitors are frequently used in computer systems in order to control noise. In general, decoupling capacitors are placed as close as possible to the devices they protect in order to minimize the amount of line inductance and series resistance between the devices and the capacitors. An integrated circuit package includes a substrate (110, 210) having a first surface (111, 211) and an opposing second surface (112, 212), and a die platform (130, 230) adjacent to the first surface of the substrate. The substrate has a recess (120, 220) therein. The integrated circuit package further includes a capacitor (140, 240) in the recess of the substrate. The presence of a recess in the substrate provides an opportunity to reduce the separation distance between a die supported by the die platform and the decoupling capacitors. A further advantage of embodiments of the invention lies in its ability to maintain socket compatibility.

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.