Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract: A multiple die structure includes a first die (110), a second die (120), a carbon nanotube (130) having a first end (131) in physical contact with the first die and having a second end (132) in physical contact with the second die, and an electrically conductive material (240) in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure (400, 500, 600, 900) in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract: Applications of smart polymer composites to integrated circuit packaging.

Abstract: A data storage medium includes a piezoelectric film (101) having a surface (111) including a halogen. In one embodiment, the halogen exists in an atomic concentration of at least approximately 10 percent. The result is a hydrophobic surface conducive to long-lasting scanning probe tips, low contamination, and stable surface charge. A data storage device incorporating the data storage medium includes an enclosure (205) containing the data storage medium and an adjacent scanning probe (230) wherein the enclosure has a relative humidity of at least approximately 40 percent and at least a portion of the scanning probe is coated with a layer of water.

Abstract: Embodiments of a heat spreader and an assembly including such a heat spreader are disclosed. The heat spreader includes a stiffening member, which in one embodiment comprises a wall extending from a lower surface of the heat spreader. The wall may be coupled with a substrate, and the addition of this wall may decrease warpage of the substrate and increase package stiffness. The wall may be located between adjacent integrated circuit die that are disposed on the substrate. Other embodiments are described and claimed.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: An underfill formulation includes a solvent (110), a plurality of amphiphilic block copolymers (120) in the solvent, and an adhesion promoter (130) in the solvent. Groups of the plurality of amphiphilic block copolymers form a plurality of micelles (140) in the solvent, with the micelles including a core (141) and a shell (142) surrounding the core, and the adhesion promoter is in the core of at least some of the plurality of micelles.

Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

Abstract: An electronic assembly comprising one or more high performance integrated circuits includes at least one high capacity heat sink. The heat sink, which comprises a number of fins projecting substantially radially from a core, is structured to capture air from a fan and to direct the air to optimize heat transfer from the heat sink. The heat sink fins can be formed in different shapes. In one embodiment, the fins are curved. In another embodiment, the fins are bent. In yet another embodiment, the fins are curved and bent. Methods of fabricating heat sinks and electronic assemblies, as well as application of the heat sink to an electronic assembly and to an electronic system, are also described.

Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.

Abstract: An apparatus capable of producing a moveable magnetic field includes a moveable support structure (110) and a magnetic field source (120) supported by the moveable support structure, where the magnetic field source is in a fixed position relative to the moveable support structure. The magnetic field source generates a magnetic field at a wafer surface of at least approximately 50 Oersted, and the magnetic field is aligned so as to produce magnetic anisotropy in a plane of the moveable support structure.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.

Abstract: A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer (111), a first metal layer (112) over the first barrier layer, a first passivation layer (113) over the first metal layer, a via structure (114) extending through the first passivation layer, a second barrier layer (115) over the first passivation layer and in the via structure, a second metal layer (116) over the second barrier layer, and a second passivation layer (117) over the second metal layer and the first passivation layer.

Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.