Abstract: A digital-to-analog converter circuit suitable for implementation as an integrated circuit in integrated-injection-logic form, and a method for regulating the collector current in a plurality of integrated-injection-logic transistors are disclosed. A plurality of switching transistors are connected to digital input terminals and the currents conducted by the plurality of switching transistors are summed to yield an analog output current. An injection bar shared by each of the switching transistors provides drive current to the plurality of switching transistors. The injection bar is also shared by one or more reference transistors, the current in which is determined by a current source. A feedback circuit is used to regulate the bias of the common injection bar such that the current conducted by each switching device corresponds to the current conducted by each reference device.

Abstract: A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementation eliminates the necessity of employing a buffer gate between subarray integrated circuit chips or cells and thus decreases propagation delays in the overall array.

Abstract: A programmable read-only memory circuit including a plurality of fusible link memory cells is disclosed in which a first auxiliary current source is employed to selectively isolate a cell location to be volatized during memory personalization and a second auxiliary current source is employed to volatize or personalize a fusable link in the selected memory cell for insuring complete volatilization of the fusible link.

Abstract: A thermally stable encapsulant for a semiconductor substrate having high voltage devices disposed therein including a coating comprising a polymer having suitable polar characteristics and a metal oxide for depleting excess electron charge and for stablizing ionic contaminants during high voltage operation.

Abstract: A bonding head particularly suitable for ultrasonic bonding of larger dimensioned wires to electrically conductive metallic regions for the semiconductor field comprising a stepped impact surface for simultaneously effecting an ultrasonic bond between the wire and metallic conductive regions. The lowermost stepped portion of the impact surface insures that the wire is maintained in a stationary or positively-held position with respect to the conductive regions so as to then allow both the stepped surfaces to transmit ultrasonic energy and insure scrubbing action between the elements to be bonded.

Abstract: A bonding head particularly suitable for ultrasonic bonding of larger dimensioned wires to electrically conductive metallic regions for the semiconductor field comprising a stepped impact surface for simultaneously effecting an ultrasonic bond between the wire and metallic conductive regions. The lowermost stepped portion of the impact surface insures that the wire is maintained in a stationary or positively-held position with respect to the conductive regions so as to then allow both the stepped surfaces to transmit ultrasonic energy and insure scrubbing action between the elements to be bonded.

Abstract: A solar fluid heater includes a first planar surfaced collector for transmitting solar energy to heat a fluid located in a plurality of passages adjacently disposed to the collector. A honeycomb convection suppressor includes sidewalls orthogonally disposed to the planar surface of the collector for reducing convection heat losses. A selective coating disposed over the planar surface reduces radiation losses. Insulator material is disposed on the bottom side of the fluid carrying passages further minimizing losses from the heated fluid or water. In a dual sided fluid heater embodiment, another honeycomb conduction suppressor is disposed on the other side of the planar surfaced collector and direct and reflected solar energy is transmitted through both a top and bottom outer cover. SPThis is a division of application Ser. No. 588,977, filed June 20, 1975, abandoned.

Abstract: A digital tone decoder includes means for generating a timing signal, zero crossing counter means for generating a decode signal after a predetermined number of zero crossings in response to an incoming time domain signal and for generating a reset signal at a predetermined time after the decode signal is sent to reset said zero crossing counter means to zero, and decoder means coupled to said zero crossing counter and to said timing means for generating an output signal at one of a plurality of output terminals corresponding to the frequency of the incoming signal upon receipt of the decode signal from said zero crossing counter means, said decoder means being reset to an initial state upon receipt of the reset signal.

Abstract: Method and structure for encapsulating or providing a package for a light emitting semiconductor device in order to prevent package failure due to chemical contaminants. A light emitting semiconductor chip is connected to terminal leads having sharp angular portions. The device and the sharp angular portions are coated with a resilient elastomeric resin material inner core. An outer core comprising an acrylic or polycarbonate plastic material is injection molded over the inner core so as to leave exposed terminal leads for interconnection to electrical substrates such as cards or printed circuit boards.

Abstract: Method and structure for encapsulating or providing a package for a light emitting semiconductor device in order to prevent package failure due to chemical contaminants. A light emitting semiconductor chip is connected to terminal leads having sharp angular portions. The device and the sharp angular portions are coated with a resilient elastomeric resin material inner core. An outer core comprising an acrylic or polycarbonate plastic material is injection molded over the inner core so as to leave exposed terminal leads for interconnection to electrical substrates such as cards or printed circuit boards.

Abstract: A circuit for eliminating transient pulses associated with the opening and closing of a mechanical contact by providing logic and memory circuit means for selectively comparing an input signal supplied from the contact terminal with the output signal from the memory means for either changing the state of the output signal or maintaining the output signal in its existing state. Only a single line connection to the contact terminal is required for supplying both the open and closed electrical signal representations of the contact position.

Abstract: The number of devices and integrated circuit area required to enter new data or to recirculate data in a charge coupled storage memory is reduced by employing separated charge source areas interconnected to selective enabling means and appropriate phasing signals.

Abstract: A clamping circuit particularly adaptable for integrated circuits having improved low impedance characteristics. The operating characteristics of a "current-mirror" clamping circuit are improved by coupling a regenerative semiconductor feedback circuit means across the transistor and diode current-mirror circuit for increasing current flow to the semiconductor diode in response to the clamping transistor being driven to a lower impedance state by voltage changes coupled to its emitter terminal.

Abstract: A system for handling plate like objects (e.g., semiconductor wafers) includes a gas actuated fixture having a surface for releasably picking up the plate like objects (e.g., by Bernoulli effect). Means is provided for moving the pickup fixture in a plane of motion from a first to second position. Means forming a part of the pickup fixture (e.g., a selectively pressured bellows) moves the pickup surface orthogonally to the plane of motion. An air track or other conveyer for the plate like objects includes means for restraining the objects beneath the first position. Means for positioning successive locations of a carrier for the plate like objects positions the successive locations beneath the second position. In operation, the system picks up the plate like objects from the conveyer, loads them onto the carrier, then unloads them from the carrier and returns them to the conveyer, all without subjecting the objects to human contamination.

Abstract: A digital FSK time rate change modulator is responsive to a digital input signal and generates either a first or a second output frequency. The FSK modulator switches from one output frequency to the other in small increments over a predetermined time interval. The FSK modulator includes means for generating a first and a second timing signal and input means for receiving the digital input signal. An up-down counter having an up-count input and a down-count input counts up and down between a first and a second state. First gating means is coupled to the output of the up-down counter and to the input means and passes the second timing signal to the up-count input when a high level digital input signal is present on the input means and the up-down counter is not in the second state.

Abstract: A method for bonding a gallium-type light emitting diode (LED) to a metallized substrate interconnection member, such as, a header, or a strip. An LED wafer is subjected to premetallizing backside processing in order to prepare the surface for a metallizing deposition step. During metallization, the backside wafer is deposited with a gold-germanium or gold-silicon alloy. Thereafter, the wafer is heated in forming gas in order to alloy the gold-germanium or gold-silicon first layer to the wafer backside. Then, a second layer of gold-germanium or gold-silicon is evaporated over the alloyed first layer. The LED chip or die is then eutectically die bonded to a metallized substrate.

Abstract: An array of integrated circuits for selectively connecting a first communication line to a second communication line which employs a latching type semiconductor memory element for selectively energizing and deenergizing the semiconductor connect or disconnect switches located in the communication path. Addressing means are selectively responsive to addressing and reset signals for activating or deactivating the semiconductor latching circuit for either opening or closing the semiconductor switch. The semiconductor latching circuit is external to the communication lines and is capable of being set by the addressing signals and deactivated by a common line in conjunction with the set signals.

Abstract: A high band width logic gate including a basic current switch logic block and emitter-follower output transistors. A switchable active circuit current sink is connected between an internal voltage switching node associated with the current switch logic gate and the emitter terminal of the emitter-follower output transistor. The active current sink is switched between a relatively low conductive state to a relatively high nonsaturating conductive state in order to maintain substantially constant current flow through the emitter-follower output transistor during switching of the logic gate in order to significantly improve AC beta roll off characteristics.

Abstract: An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.

Abstract: A driver circuit that permits full duplex transmission of digital data on a single signal line includes means for enabling a receiver of a station having a transmitter and a receiver to ignore outgoing digital signals from the transmitter of the same station and receive incoming signals. The circuit includes means that combine the incoming and outgoing digital signals in the signal line to form a composite multi-level signal which shifts between predetermined amplitude levels and means that recover the incoming digital signals from the composite signal. An offset bias level is added within the receiver signal processing to the transmitter pulse level to reduce noise susceptibility. Using such a circuit a full duplex transmission system of a plurality of stations connected to a common single signal line is provided. Such a system can be operated in a broadcast mode wherein one station can transmit signals to the remainder of stations.