Abstract: A display system for providing a real-time, dynamic presentation of an analog signal waveform is disclosed. The system includes an A-D converter that, in turn, drives a serial string of binary weighted bubble domain generators. The bubble domain generators generate moving columns of bubble domains, the total amplitude of light that is provided by each column representing the amplitude of the analog signal waveform at each of an associated sample time. The bubble domain memory plane is of a construction to permit the columns of moving bubbles to appear as moving columns of bright spots when seen by an observer using a plane polarized light beam and an analyzer.

Abstract: A method of and an apparatus for reading out the informaton that is stored in the magnetizable layer of a cross-tie wall memory system is disclosed. A first embodiment of the apparatus utilizes: a conductive probe, that along its length and is conductively coupled to the magnetizable layer and the tip which is centered at or near the Bloch-line position in the memory segment of the cross-tie wall; a conductive crescent that is oriented concentric to the probe tip and that along its length is conductively coupled to the magnetizable layer; and a readout device that is coupled across the probe and crescent for determining the resistance in the magnetizable layer between the probe tip and crescent as an indicaton of the existence or non-existence of a Bloch-line in the memory segment.

Abstract: A method of and an apparatus for obtaining double bit error correction capabilities in a large scale integrated (LSI) semiconductor memory system using only single bit error correction, double bit error detection (SEC, DED) logic are disclosed. The method is based upon the statistical assumption that in a large scale integrated semiconductor memory, substantially all errors in the data bits that make up a data word are initially a single bit error and that increasing multiple, i.e., double, triple, etc., bit errors occur in a direct increasing ratio of the use or selection of the data word. In the present invention, all data words are priorly tested to be error free. Subsequent detection of single bit errors results in the correction of the single bit error and the storage of the single bit error correcting syndrome bits in a syndrome bit memory.

Abstract: A data track formed of a strip of magnetic film having substantially zero uniaxial anisotropy, i.e., isotropic, for a cross-tie wall memory system is disclosed. The data-track-defining-strip of isotropic magnetic film utilizes its shape, i.e., its edge contour induced anisotropy, rather than its easy axis magnetic field induced anisotropy, to constrain the cross-tie wall within the planar contour of the film strip. The use of the shape induced anisotropy of an isotropic strip of magnetic film permits the use of nonlinear, i.e., curved, data tracks which curved data tracks were not permitted by the prior art cross-tie wall memory systems that were limited to the use of anisotropic magnetic film.

Abstract: An improved sense latch circuit for differentially sensing an MNOS memory FET's voltage thresholds, selectively operable in either a memory retention or read interrogation mode with enhanced sensitivity and improved power conservation. The improvement consisting of the additional cross coupling of each of the latch outputs to a respective plurality of MOS FETs coupled in series with each of the MNOS FET inputs, which cross coupling reduces extraneous current paths and increases the switching sensitivity of the sense latch circuit.

Abstract: The present invention relates to a memory addressing mechanism which has been formulated to accommodate three address structures: real, based and virtual. To accomplish this result the address generation function in the memory addressing mechanism has been separated into two distinct parts, address computation and address translation. By merely changing the hardware components in the address translation part of the memory addressing mechanism and leaving the hardware in the address computation part constant, an optional memory addressing mechanism which supports either a real address structure, a based address structure or a virtual address structure can be implemented.Further, the present invention with the virtual address translation apparatus in cooperation with the fixed address computation apparatus provides a virtual addressing mechanism which will compute and retrieve a memory word utilizing a four-segment memory address with only two memory references.

Abstract: Defining the structuring of bubble domains in the magnetizable layer of a bubble domain memory plane is determined by modification of the magnetic characteristics of the magnetizable layer in the confinement area. The memory plane is comprised of a non-magnetic Gadolinium Gallium Garnet (GGG) layer which is a supporting substrate upon which is formed by the liquid phase epitaxy (LPE) method a magnetizable layer in which bubble domains are capable of being generated, sustained and moved about. Formed upon the bubble domain supporting magnetizable layer is a matrix array of conductive drive lines, the intersections of which define respective memory areas. In each memory area the position of the bubble domain in the magnetizable layer is determined by modifying the magnetic characteristics of the magnetizable layer in a confinement area as by an ion milling process. The ion milled confinement area along the line of the thickness gradient generates a perpendicular field H.sub.

Abstract: This invention relates to an apparatus and method for preventing a digital computer from erroneously outputting data contained in an output word to another digital computer or peripheral device. A portion of the output word is allocated as a key field which must be matched with a predetermined lock value before the digital computer will allow an output of the data field of the output word to occur. That is, a key value specified as part of the output word must match a predetermined lock value before an output transfer of the data field of the output word is allowed to take place. If the lock value and key value do not match, the central processor section of the digital computer is interrupted. This apparatus and method not only verifies the correct operation of the digital computer output data transfer hardware by preventing an erroneous transfer of the data field of the output word but also alerts the central processor section in the event of a mismatch by means of an interrupt.

Abstract: A system for optically correlating two signals, e.g., radar, sonar, etc., incorporating both time shifts and doppler shifts is described. The correlation of the signals is produced as a two-dimensional distribution of light on a light detector/display plane wherein the amplitude of the light distribution is proportional to the correlation of the two signals as a function of relative time shifts, .DELTA.t (X direction), and relative doppler shifts, .alpha..omega. (Y direction), between the signals. Doppler shifts are introduced into the processor by the incorporation of a channelized cylindrical lens in one signal channel while using a cylindrical lens in the other signal channel.

Abstract: A laminated, integral structure that forms a bubble memory plane for the generation, storage and transfer of single wall domains, bubble domains or bubbles is disclosed. The memory plane is formed of a non-magnetic gadolinium gallium garnet (GGG) support member; formed upon the support member is a magnetizable layer that is capable of sustaining stripe domains; formed upon the stripe domain layer is a non-magnetic gadolinium gallium garnet (GGG) spacer layer; and, formed upon the spacer layer is a magnetizable layer in which single wall domains or bubbles are capable of being generated, sustained and transferred from one position to another along a planar dimension of the bubble domain layer.

Abstract: Defining the structuring of bubble domains in a magnetizable layer of a bubble domain memory plane is determined by modifying the magnetic characteristics of the magnetizable layer in the confinement area. The bubble domain memory plane is comprised of a non-magnetic Gadolinium Gallium Garnet (GGG) layer which is a supporting layer upon which is formed by the liquid phase epitaxy (LPE) method a plurality of magnetizable layers in each of which a bubble domain is capable of being generated and sustained. Upon the memory plane are formed, as by any of many well-known deposition techniques, a matrix array of a parallel set of horizontally oriented X drive lines and an orthogonally oriented parallel set of Y drive lines. Each X drive line, Y drive line intersection of the matrix array defines a memory area having four quadrants.

Abstract: A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse.

Abstract: An apparatus for and a method of moving stripe domains in a direction transverse their length is disclosed. The apparatus includes a layer of magnetizable material in which stripe domains are capable of being generated, sustained and moved. Formed upon the magnetizable layer are two parallel contiguous disk files, each of which is formed of a plurality of linearly aligned similar contiguous Bicore disks. Each Bicore disk is comprised of a disk of a relatively soft magnetizable material, e.g., Permalloy, and a superposed disk of a relatively hard magnetizable material, e.g., Cobalt, sandwiching an insulative layer, e.g., silicon dioxide, SiO.sub.2, therebetween.

Abstract: This invention relates to a clock sequencing apparatus which allows for clock stoppage at the end of a particular clock sequence without a false decoding of clock pulses at the beginning of what would have been the next clock sequence. This result is accomplished by providing a multi-state sequential apparatus having more states than clock phases. The apparatus will detect a stop condition on the last clock phase of a clock sequence and instead of changing to the state associated with the first clock phase of the next clock sequence, it will instead change state to one or more additional "dead time" states which will allow other logic circuitry to discontinue gating of the clock phases before the apparatus returns to the state associated with the first phase of the next clock sequence. The apparatus will then remain at the state associated with the first phase of the next clock sequence until the clock is restarted and the process is repeated.

Abstract: Disclosed is an apparatus for and a method of propagating bubble domains along fixed guidance channel forming stripe domains by capturing them in moveable stripe domains and then moving the capturing moveable stripe domains. The memory plane comprises a non-magnetic Gadolinium Gallium Garnet (GGG) layer which is a supporting substrate upon which are successively formed by the liquid phase epitaxy (LPE) method: a first stripe domain layer, a first non-magnetic spacer layer; a bubble domain layer; a second non-magnetic spacer layer; a second stripe domain layer; and a third non-magnetic spacer layer upon which is formed the necessary propagation circuitry.

Abstract: An apparatus for and a method of propagating bubble domains is disclosed. The apparatus includes a memory plane that is comprised of a non-magnetic support member upon which are formed a bubble domain layer and at least one stripe domain layer. The stripe domain layer has a set of relatively-narrow, periodic, potential well generating fixed stripe domains provided therein while the bubble domain layer has a set of relatively-wide, parallel, potential well generating fixed guidance channels provided therein that are oriented orthogonal to the parallel set of stripe domains in the stripe domain layer. Bubble domains are concurrently entered, in parallel, at one end of the memory plane in selected ones of the guidance channels. A periodic amplitude modulated bias field of frequency F propagates each of the bubble domains along the associated guidance channel from adjacent to next downstream adjacent stripe domain and thus through the memory plane at the frequency F.

Abstract: A convergence correction system is disclosed for digitally controlling the convergence correction signals applied to the convergence correction coils of a color CRT. The convergence correction signals correspond to a plurality of segments defined for the phosphor face of the CRT, so as to produce the convergence of the associated electron beams at the phosphor triads within the individual segments. The system provides for the independent adjustment of the convergence of each electron beam within each of the four quadrants of the phosphor face, independent of the adjustments for the convergence of the other electron beams. The system further provides for the use of only one convergence correction coil for each associated electron beam.

Abstract: An apparatus for and a method of providing error correction of the address word of a cache memory system (CMS) utilizing post-write storage of the least recently used (LRU) block of data words. Error correction circuitry (ECC) is provided at the output of the address buffer (CAB) portion of the cache memory system so that the address word that specifies the addressable location in the main storage unit (MSU) into which the block of data words, which block of data words is stored in the data buffer (CDB) portion of the cache memory, is to be stored or written-back is error corrected upon readout. This error correction of the address word ensures that correctable errors in the address buffer provided address words do not generate a Miss signal by the storage interface unit (SIU) which, in turn, requires a MSU reference even though the desired address word and the associated data word are available in the cache memory system.

Abstract: A display system for providing a real-time, dynamic presentation of an analog signal waveform is disclosed. The system includes an A-D converter that is coupled to a 1-out-of-M decoder that, in turn, drives a serial string of bubble domain generators. The bubble domain generators generate moving columns of bubbles, the heights of the columns representing the amplitudes of the analog signal waveform at each of the associated sample times. The bubble domain memory plane is of a construction to permit the columns of moving bubbles to appear as moving columns of bright spots when seen by an observer utilizing a plane polarized light beam and an analyzer.

Abstract: This invention relates to a right justified mask transfer apparatus which may be effectively utilized in a digital data computer. A right justified mask transfer register is provided which holds the result of a logical bit-by-bit ANDing of a multi-bit data word with a multi-bit mask work such that only those bit positions for which the mask word are of a predetermined binary significance are collected contiguously in the mask transfer register, all other bit positions being ignored. Further operations on intermediate digital data computations may be more easily performed by utilizing the right justified mask transfer function to select certain data bits or fields.