Abstract: An electrically and mechanically modular design of a high impedance, passive transceiver is disclosed for use in distributed, serial transmission systems to provide half uplex interfacing to multiple users with minimum loading and reflection. The transceiver is selectively operable in either of two modes: a receive mode for receiving low-level serial, bi-phase (3 state) Manchester coded signals and transmitting (2 wire, 2 state) signals at transistor-transistor logic (TTL) levels; and a transmit mode for receiving (2 wire, 2 state) signals at TTL levels and transmitting the low-level, serial bi-phase, (3 state) signals on the bus.

Abstract: Inverter power supply control circuitry that protects power supply components from relatively quick-changing over-current conditions and that provides regulation of the power supply's output current upon relatively slow-changing load conditions.

Abstract: Disclosed is a cross-tie wall memory system for the generating, propagating and detecting of binary data represented by the presence or absence of cross-tie, Bloch-line pairs along a cross-tie wall in a thin magnetic data track. The system includes a three-level shift register structure comprised of the following layers: first and second substantially similar, serrated-edged current conductive striplines and a serrated-edged thin magnetic layer data track. The shift register is terminated on one end by a cross-tie, Bloch-line pair generator and on the other end by a cross-tie detector. A data word is stored in the data track between the generator and the detector and is shifted through the detector for readout of the stored data word. The first and second serrated-edged striplines are formed of alternate wide-narrow portions with the wide portion of one stripline oriented above/below the narrow portion of the other stripline.

Abstract: Disclosed is a cross-tie wall memory system for the generating, propagating and detecting of binary data represented by the presence or absence of cross-tie, Bloch-line pairs along a cross-tie wall in a thin magnetic layer. The system includes a three-level structure comprised of the following superposed layers: a straight-edged current conductive stripline; a serrated-edged thin magnetic layer data track, and a wide-narrow-edged current conductive stripline terminated on one end by a cross-tie, Bloch-line pair generator. A cross-tie detector is positioned intermediate the ends of the data track and is sandwiched between the data track and the wide-narrow-edged current conductive stripline. An N-bit data word is stored in the data track between the generator and the detector, is shifted through the detector for readout of the stored data word and is then restored into its original stored position by being shifted in a reverse manner along the data track and back through the detector.

Abstract: Apparatus for correcting memory errors by testing the addressable location causing the memory error in realtime. The memory responds to read requests by accessing the contents of the requested addressable location. If the contents of the addressable location contain errors, which are uncorrectable by other means, the memory saves the erroneous data word and the requested addressable location is tested by immediately writing into and reading from the requested addressable location. Two data words are sequentially written into and read from the requested addressable location which cause both a one and a zero to be written into each bit position of the requested addressable location. If the reads reveal an error at any bit positions of the requested addressable location, the corresponding bit positions of the erroneous data word are complimented and the resultant is transferred to the requestor using the normal data path.

Abstract: Configurations of Boolean elements for implementing a sequential GF(2.sup.n) Galois multiplication gate are disclosed. Each configuration includes a single subfield GF(2.sup.m) Galois multiplication gate, where m is a positive integral divisor of n, e.g., n=8 and m=2, and assorted controls. Also disclosed is a sequential implementation of a GF(2.sup.n) Galois linear module as described in the J. T. Ellison Pat. No. 3,805,037 wherein the controls of the sequential GF(2.sup.n) multiply gate cause the Galois addition (bit-wise Exclusive-OR) of an n-bit binary vector, Z, to the final Galois product.

Abstract: An inverter power supply circuit that compensates for variations in the power supply's output voltage, which variations are due to variations in output loading, is disclosed. The input side of the circuit's DC-DC Converter-Inverter-Converter coupling transformer incorporates a compensation network having an impedance that is equivalent to the power supply's output impedance. Variations in the output loading cause corresponding proportional changes in the currents passing through the load and the compensating network. The changing current in the compensating network on the input side of the coupling transformer generates a corresponding changing voltage that is coupled, as a positive feedback, to the chopping transistor of the power supply to provide compensation for the variation in loading on the output side of the coupling transformer.

Abstract: Disclosed is a cross-tie wall memory system for the generating, propagating and detecting of binary data represented by the presence or absence of cross-tie, Bloch-line pairs along a cross-tie wall in a thin magnetic layer. The system includes a three-level structure comprised of the following superposed layers: a straight-edged current conductive stripline; a serrated-edged thin magnetic layer data track, and a wide-narrow-edged current conductive stripline terminated on one end by a cross-tie, Bloch-line pair generator and on the other end by a cross-tie detector.

Abstract: A method of and an apparatus for magneto-resistively detecting information in a cross-tie memory system is disclosed. The detector includes a first conductive element, which is the terminating portion of an electrically-conducting wide-narrow edged propagating drive line, and second and third conductive elements that are serially aligned along a magnetic, serrated-edged data track, which three conductive elements form two gaps therebetween. The two gaps are oriented along the data track at respective narrow portions, a first narrow portion which may support a cross-tie but which second narrow portion will not support a cross-tie. A differential sense amplifier is coupled across the two gaps using the second narrow portion as a reference segment to differentially detect the presence vel non of a cross-tie in the first narrow portion.

Abstract: Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A virtual memory data processing system permits a computer program to specify relative (or virtual) addresses rather than physical (or real) addresses. Most practical virtual memory data processing systems utilize a Virtual Address Translator (VAT), often called a Directory Look-Aside Table (DLAT). The VAT contains a plurality of internal conversion tables which perform virtual address to real address translation. A binary code, called the Interrupt Level Code (ILC), is appended to the virtual address of entries within the plurality of internal conversion tables within the VAT to permit the VAT to translate virtual addresses to real addresses only if the present Central Processing Unit (CPU) interrupt level state corresponds to the interrupt level state denoted by the ILC within the VAT.

Abstract: A method of and an apparatus for selectively isolating digital data bus drivers from digital data busses for fault recovery and diagnostic purposes. The digital data bus drivers may be either transistor-transistor logic (TTL) or emitter coupled logic (ECL). For TTL digital data bus drivers, the input voltage (V.sub.CC) is supplied via a switching power transistor. For ECL digital data bus drivers, the ground connection (V.sub.CC1) is made via a switching power transistor. In either case, the switching power transistor is turned on and off in response to one binary bit in an isolation register coupled to the power transistor via an open collector gate or electromechanical switch. By supplying the V.sub.CC (for TTL) or V.sub.

Abstract: A voltage regulation loop for the rejection of line frequency ripple of 0-180 Hz in an inverter power supply is disclosed. The loop includes an error amplifier (E), a pulse-width modulator (P), an inverter (I), a second summing node (N.sub.2), an output filter (F), and a feedback loop back to a first summing node N.sub.1 at the error amplifier. The novel pulse-width modulator is non-linearly operated to provide an improved rejection of the power supply's line frequency ripple and an improved stability.

Abstract: Apparatus for determining the next data word of a requested block of data words in interlaced rotating mass memories to enable transfer of the requested block from other than the first word in the block to reduce the effective average latency. The system assumes the use of a memory storage element which is read in a serial rotational fashion (e.g., drum, disk, charge coupled device, etc.). The present invention compares the address of the data requested by a Central Processor Unit (CPU) with the address from the interlaced memory storage element that indicates its present rotational position. From these addresses, it computes the address of the next accessible cell within the requested block and transfers that address to the CPU to enable it to access the requested block at the earliest possible time.

Abstract: A display system using the dispersive Faraday coefficient of a magnetic screen to obtain a color display from white light is disclosed. A beam of energy is directed upon a magnetic screen while concurrently an intensity modulated magnetic field is directed normal to the surface of the magnetic screen. The combination of the heating effect of the energy beam and the magnetic orienting effect of the intensity modulated magnetic field established localized areas of differing magnetic characteristics over the planar surface of the magnetic screen. Subsequently, a polarized beam of white light that floods the magnetic screen is, for each of several wave lengths, differently rotated upon passing through each of the areas of differing magnetic characteristics in the magnetic screen. The beamlets that are formed by the so-differently rotated areas of the polarized white light beam are then passed through an uncrossed analyzer, which beamlets appear as a multicolored projection upon the magnetic screen.

Abstract: Apparatus for avoiding ambiguous data in a multi-requestor computing system of the type wherein each of the requestors has its own dedicated cache memory. Each requestor has access to its own dedicated cache memory for purposes of ascertaining whether a particular data word is present in its cache memory and of obtaining that data word directly from its cache memory without the necessity of referencing main memory. Each requestor also has access to all other dedicated cache memories for purposes of invalidating a particular data word contained therein when that same particular data word has been written by that requestor into its own dedicated cache memory. Requestors and addresses in a particular cache memory are time multiplexed in such a way as to allow a particular dedicated cache memory to service invalidate requests from other requestors without sacrificing speed of reference or cycle time of the particular dedicated cache memory from servicing read requests from its own requestor.

Abstract: An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory array within the memory module. A status register located within the memory module has two bit positions assigned to controlling the closed loop address capability. If the two assigned bit positions contain binary zeroes, the memory module operates normally by using each address received to address one addressable location of the memory array of the memory module. If one of the assigned bit positions contains a binary one, subsequent read commands cause the memory not to access the memory arrays but to return the portion of the address corresponding to the bit position containing the binary one (i.e.

Abstract: Apparatus for providing a closed loop data path within a memory module to enable a central processing unit (CPU) to test the error correction circuitry of the memory module under software control without the necessity of accessing the memory arrays within the memory module. The memory module has error correction circuitry providing single bit correction/double bit detection. The error correction circuitry generates an error code which is appended to each data word upon being written into the memory array of the memory module. The error correction circuitry uses the error code to detect and correct errors in each data word read from the memory array of the memory module. A status register within the memory module stores control and status information for communication between the central processing unit and the memory module. Two bit positions of the status register are dedicated to closed loop error correct. If both bit positions contain binary zeroes, the memory module operates normally.

Abstract: A printed circuit board guide spring having spring members for securing the printed circuit board and the guide spring within guide slots in a heat sink.

Abstract: A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group.

Abstract: A method of and a detector for magneto-resistively reading out the information that is stored in a cross-tie wall memory system. The detector includes two current conductive elements that are positioned along and across the cross-tie wall in a magnetic film that is configured into a data track for sandwiching a plurality of memory cells therebetween. A separate current conductive element is centered over each of the sandwiched memory cells for conducting the read current drive signal out of the data track in the area of the Bloch-line, but forcing the read current drive signal through the data track in the area of the cross-tie. A stored binary 1, represented by a cross-tie, Bloch-line pair, is propagated into one end of the detector and is replicated in all of the sandwiched memory cells; conversely, a stored binary O, represented by the absence of a cross-tie, Bloch-line pair, would be replicated in all of the sandwiched memory cells.