Abstract: A loop filter for a phase locked loop system having a voltage controlled oscillator (VCO), a divide-by-N circuit responsive to the output of the VCO, and an edge sensitive phase/frequency comparator responsive to the output of the divide-by-N circuit and a reference timing signal for providing a first control signal when the output of the divide-by-N circuit lags the reference timing signal or a second control signal when the output of the divide-by-N circuit leads the reference signal. The loop filter specifically includes first and second capacitors serially coupled between an output node and a ground reference node, wherein the second capacitor is connected to the ground reference node and the output node provides a control voltage to the VCO. A first current source is controllably connected by a first switch to the output node in response to the first control signal, whereby the first current source charges the first and second serially coupled capacitors.

Abstract: A substrate contact structure which includes a plurality of contact pads formed on a surface of the substrate and located for receiving a predetermined integrated circuit chip or die having conductive bonding bumps corresponding to and respectively associated with the plurality of contact pads. Each of the contact pads includes a plurality of bonding sites, wherein the pattern of bonding sites is substantially identical for each of the contact pads. Each bonding site has corresponding bonding sites on the other contact pads which cooperatively form sets of bonding sites, each of which is a mirror image of the conductive bonding bumps on the predetermined integrated circuit chip. Methods of producing substrates suitable for removal and replacement of bump bonded integrated circuit chips, as well as methods of repair of such structures are also disclosed.

Abstract: A process for forming electrically conductive circuitry on a metallic nonconductive substrate or insulating layer which includes the steps of providing a nonconductive ceramic substrate having a metallic component and which can dissociate into its constituent components to provide dissociated metal bonded to the ceramic substrate upon application of laser energy. Laser energy in then applied to predetermined areas of the surface of the nonconductive ceramic substrate to provide dissociated metallic conductors in the predetermined areas. The disclosed process further includes the formation of metallized through holes by application of laser energy to the nonconductive ceramic substrate to form a through hole, whereby dissociated metal in formed on the inside of the through hole. The disclosed process also includes the capability to down trim a thick film or thin film resistor which is conductively coupled between two areas of metallization.

Abstract: A method of making a chip carrier array including the steps of providing a ceramic substrate and forming elongated slots in the substrate which define the edges thereof and which form one severable interconnecting bridge at each edge of each chip carrier, which bridges maintain the individual chip carriers in the array. A plurality of edge interconnect conductors are formed along each edge portion of each chip carrier on either side of the interconnecting bridges.

Abstract: An infrared detector assembly is disclosed which includes a photosensitive layer (111) and a first planar contact structure (113) conductively coupled to the photosensitive layer for collecting charge carriers generated by radiation incident on the photosensitive layer. The detector assembly further includes a second planar contact structure (119) substantially coextensive with and separated from the first planar contact structure. A dielectric layer (115) separates the first and second planar contact structures. The first and second planar contact structures and the dielectric structure form a feedback capacitor which is integral with the detector assembly and which provides feedback capacitance for an externally provided amplifier.

Abstract: A process is disclosed for filling vias in a sheet of dielectric tape for use in fabricating hybrid multilayer circuit structures. The process includes the steps of securing a sheet of dielectric tape (11) comprising a dielectric layer and a supporting carrier layer to a frame (13), forming vias (19) in the dielectric tape, securing the frame with the dielectric tape to a via filling fixture (17), filling the vias with via fill metallization, and removing the dielectric tape from the via filling fixture. The process further contemplates filling vias of dielectric tape secured directly to an exposed surface of a hybrid circuit during the manufacturing process.

Abstract: A pick and place head for transferring die or chips containing electronic circuitry from waffle packs to substrates prior to lead bonding operations. The pick and place head includes a spindle rotatably mounted at the end of an arm and carrying jaws which are extendable to grasp, retract and rotate a collet having a vacuum pickup tip. Embodied as part of the spindle is a vacuum sensor manifold which sealably receives the collet and cooperates with it to form part of a vacuum sensing system to detect pickup of the chip or die.

Abstract: A technique is disclosed for trimming resistors and other passive circuit components buried in hybrid multilayer circuit structures. For example, resistors (13) are formed between two dielectric layers (11, 19) of a hybrid multilayer circuit structure (10). The multilayer circuit structure with the buried resistors is appropriately processed to provide a fired multilayer circuit structure. Trimming of the buried resistors is accomplished with a laser beam that cuts through dielectric material of the fired circuit structure to selectively remove part of the resistive material of the buried resistors. The values of the buried resistors may be tested with conductive elements (15, 17) that are conductively coupled to the buried resistors. The disclosed technique also contemplates the trimming of other buried passive circuit components such as capacitors, and further contemplates the use of other trimming methods such as abrasive, air jet, or water jet trimming.

Abstract: Method and apparatus for the tunable generation of new wavelengths of optical radiation from input sources of predetermined wavelength. Optical radiation from a source (20), or sources, is launched into both the fast and slow axis of a birefringent optical waveguide (12) as pump waves. The pump waves generate new Stokes and anti-Stokes waves through enhanced four photon mixing processes. The Stokes wave is wavelength or frequency shifted from the pump wave by a small amount and exits the end of the optical waveguide (12) where it can be interfaced to various apparatus for utilization. The apparatus preferably employs polarization control means for controlling the polarization of optical radiation launched into the birefringent optical waveguide. The waveguide can also be an optical fiber or planar waveguide structure. The wavelength or radiation generated and output can be tuned by altering the birefringence of the waveguide.

Abstract: A process for fabricating semiconductor integrated circuits which include active regions having well defined mesa structures which maintain their size during processing. Mesa structures are formed in the top portion of a semiconductor substrate, and an insulating layer is formed on the top portion of the semiconductor. Active regions are defined in the semiconductor substrate which include the mesa regions where active devices are to be formed, the remaining regions of the semiconductor substrate being non-active regions. Photoresist is selectively applied on the insulating layer over the non-active regions to maintain exposed insulating layer portions over the mesa structures. The photoresist and the exposed insulating layer portions are etched to thin or remove the exposed insulating layer portions while maintaining the thickness of the covered insulating portions.

Abstract: A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.

Abstract: A technique is disclosed for obtaining a self-aligned twin-well structure in a CMOS process. A double layer of two different photoresist materials is employed to obtain an overhang photoresist structure used for the p-well masking and ion implantation process. After the p-well implantation, pure aluminum is deposited over the wafer, forming a first layer over the p-well region and a second layer over the photoresist layers. A metal lift-off procedure is performed to dissolve the photoresist layers and thereby remove the second layer of metal. The first layer of aluminum remaining on the wafer forms a conjugate of the p-well pattern and serves as the n-well mask for ion implantation. The invention provides a straightforward method for achieving the self-aligned twin-well structure in CMOS processes, and is adapted to high energy ion implantation for achieving retrograde impurity profiles.

Abstract: A technique is disclosed for making the high current-carrying electrical interconnections to the power FET devices in a synchronous rectifier circuit with extremely low lead resistance. All such interconnections are made with solder and pliable copper straps instead of by conventional wire bonds.

Abstract: A chip carrier array (10) is disclosed which includes interconnected chip carriers (11) separated from each other and from the substrate waste edge (25) by elongated slots (15) which define outer edges of the chip carriers (11). More particularly, each chip carrier (11) includes corners which are defined by the elongated slots (15). Each chip carrier (11) includes a plurality of electrically isolated edge interconnects (19) which wrap around edges defined by the elongated slots (15).

Abstract: A laser apparatus (10) has a coherent master oscillator radiation source (30) for driving a plurality of laser gain elements (20) positioned in a operationally parallel configuration so as to receive unamplified radiation (40) from master oscillator (30) and transmitting amplified radiation (44). Input means (60) couples portion of radiation (40) from master oscillator to each of said gain elements (20). Phase conjugate reflector means (80) operatively coupled to gain elements (20) reflects the phase conjugate of amplified radiation (44) back into the gain elements (20) where it is further amplified. Output coupling means (90) couples amplified radiation from the plurality of gain elements (20) out of the laser apparatus as a single coherent output beam of radiation.

Abstract: An infrared detector has its sensor chip assembly (10,12,14) cooled to a relatively low temperature required for its operation, whereas a preamplifier (56) required to be positioned close to the sensor chip assembly and which generates considerably more heat than does the sensor chip assembly, is thermally isolated from the sensor chip assembly and its support (16) and is cooled to a higher temperature to thereby significantly reduce the power dissipated to the coldest refrigerator stage (90).

Abstract: A timing circuit is disclosed for use with an external circuit that provides a precharge/evaluation complete signal indicative of precharge completion and evaluation completion. The timing circuit is responsive to a clock signal and the precharge/evaluation complete signal provided by the external circuit, and includes a clock enabling circuit responsive to the clock signal and the precharge/evaluation complete signal for providing a clock enable signal having first and second states respectively indicative of (a) a predetermined condition wherein evaluation has been completed and the clock signal is at a predetermined level, and (b) precharge completion.

Abstract: Ceramic package (10) for compensated crystal oscillator has a three-layer body with a closed bottom upper cavity (24), a closed bottom lower cavity (38), and a through cavity (44) in which is mounted oscillator crystal. The upper cavity carries oscillator network on thin film hybrid (68) while the lower cavity carries the temperature compensation network on thick film hybrid (70). After the components are installed and connected, the oscillator network is adjusted, and then the crystal is adjusted in vacuo. The crystal cavity is closed with thermocompression bonded covers to maintain the vacuum and the oscillator network cavity is filled with dry inert gas and is sealed by attaching a cover by thermocompression bonding. With both cavities sealed, the compensator network is adjusted as required. Thereupon, the compensation network is also covered and hermetically sealed.

Abstract: Associative holography memory apparatus is disclosed which employs a hologram, two phase conjugate mirrors, and a two-wave mixing contra-directional coherent image amplifier. The mirrors and amplifier are arranged to form a conjugate resonator whereby the output image from the apparatus tends to converge to that stored image most closely associated with an input image. Alternate embodiments are described which employ a multiple storage and erasure hologram, and which employ only a single phase conjugate mirror.

Abstract: A column shorted and full array shorted functional plane for simultaneously transferring, or shorting, data to and from the data exchange subsystems of the array processor. This functional plane nominally includes an array of pseudo-modules that architecturally corresponds to the module arrays of the other functional planes of the array processor. Thus, a pseudo-module is present in each of the elemental processors. These pseudo-modules are associated as columns that are each interconnected by a shorted plane column data exchange subsystem. These columns are, in turn, associated with column control logic circuits that each include a column memory register. A mode decode logic circuit establishes the operating configuration of the column control logic circuits.