Patents Represented by Attorney Kevin B Jackson
  • Patent number: 8319323
    Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: James P. Letterman, Jr., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
  • Patent number: 8247296
    Abstract: A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8168933
    Abstract: An image sensor having shield structures and methods of forming the same are provided. Generally, the image sensor includes: (i) substrate having at least one photosensitive element formed therein; (ii) a dielectric layer overlying the substrate and the photosensitive element; and (iii) an annular reflective waveguide disposed in the dielectric layer above the photosensitive element to reduce cross-talk between adjacent elements of the sensor while increasing sensitivity of the sensor. In certain embodiments, the sensor further includes a photoshield disposed in the dielectric above the photosensitive element and about the waveguide to further reduce the possibility of cross-talk. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 1, 2012
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Jeong Soo Byun, Vladimir Korobov, Oliver Pohland
  • Patent number: 8115273
    Abstract: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 14, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter Moens, Filip Bauwens, Joris Baele
  • Patent number: 8110787
    Abstract: An image sensor having shield structures and methods of forming the same are provided. Generally, the image sensor includes: (i) substrate having at least one photosensitive element formed therein; (ii) a dielectric layer overlying the substrate and the photosensitive element; and (iii) an annular reflective waveguide disposed in the dielectric layer above the photosensitive element to reduce cross-talk between adjacent elements of the sensor while increasing sensitivity of the sensor. In certain embodiments, the sensor further includes a photoshield disposed in the dielectric above the photosensitive element and about the waveguide to further reduce the possibility of cross-talk. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: February 7, 2012
    Assignee: ON Semiconductor Trading, Ltd
    Inventors: Jeong Soo Byun, Vladimir Korobov, Oliver Pohland
  • Patent number: 8106436
    Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: January 31, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Gary H. Loechelt, John Michael Parsey, Jr., Mohammed Tanvir Quddus
  • Patent number: 8021947
    Abstract: In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, James Sellers, Prasad Venkatraman
  • Patent number: 7960781
    Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: June 14, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Peter J. Zdebel
  • Patent number: 7953175
    Abstract: A method for applying spread spectrum noise reduction techniques to USB specifically USB2.0 communications systems includes the step of generating a base (seed) frequency for the USB system, modulating the base (seed) frequency with a spread spectrum (SS) characteristic, and utilizing (as-is, not modified) the existing ASIC that multiplying the now modulated base (seed) frequency to generate the USB standard frequency signaling rate of 480 MHz with the SS characteristic within the USB standard specification for frequency deviation.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: May 31, 2011
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Dan Hariton, Narendar Venugopal, Duoc Nguyen, Santosh K. Panigrahi, Gautam K. Singh, Sushl Kumar
  • Patent number: 7948033
    Abstract: In one embodiment, a device is formed in a region of semiconductor material. The device includes active cell trenches and termination trenches each having doped sidewall surfaces that compensate the region of semiconductor material during reverse bias conditions to form a superjunction structure. The termination trenches include a trench fill material that enhances depletion region spread during reverse bias conditions.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Zia Hossain
  • Patent number: 7943466
    Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shanghui Larry Tu, Gordon M. Grivna
  • Patent number: 7944044
    Abstract: In one embodiment, a packaged semiconductor device having enhanced thermal dissipation characteristics includes a lead frame structure and a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged semiconductor device further includes a non-planar, stepped or undulating attachment structure coupling the current carrying electrode to the lead frame. A high thermal conductivity mold compound and thin package profile further enhance thermal dissipation.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francis J. Carney, Michael J. Seddon
  • Patent number: 7915672
    Abstract: In one embodiment, a structure for a semiconductor device having a trench shield electrode includes a control pad, control runners, shield runners, and a control/shield electrode contact structure. The structure is configured to use a single level of metal to connect the various components. In another embodiment, a shield runner is placed in an offset from center configuration.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 7901990
    Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: James P. Letterman, Jr., Kent L. Kime, Joseph K. Fauty
  • Patent number: 7902601
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna
  • Patent number: 7902075
    Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Gordon M. Grivna, Gary H. Loechelt, John Michael Parsey, Jr., Mohammed Tanvir Quddus
  • Patent number: 7875950
    Abstract: In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shanghui L. Tu, Fumika Kuramae
  • Patent number: 7820528
    Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
  • Patent number: 7821063
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Robert B. Davies, David H. Lutz
  • Patent number: 7799640
    Abstract: In one embodiment, a method of forming a semiconductor device with trench charge compensation structures includes exposing the trench sidewalls to a reduced temperature hydrogen desorption process to enhance the formation of monocrystalline semiconductor layers.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 21, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: John M. Parsey, Jr., Gordon M. Grivna, Shanghui L. Tu