Abstract: In one embodiment, a turn-on delay control structure (30) includes a sense FET device (31) that is coupled to a switch node (13) in a synchronous DC-DC converter (10). The DC-DC converter includes a high-side switch (11) and a low-side switch (12). The sense FET device (31) senses current conduction in a body diode (18) of the low-side switch (12). A current sensing/comparator circuit (32) coupled to the sense FET (31) detects changes in current conduction. A delay circuit (33) and a clock/logic circuit (32) coupled to the current sensing/comparator circuit (32) predict and adjust delay time in switching between the high-side switch (11) and the low-side switch (12).

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A transistor (10) is formed as a matrix of transistor cells (13) that have drain metal strips (50) for contacting drains (15) of the transistor cells and source metal strips (55) for contacting sources (35) of the transistor cells. An interconnect layer (1030) overlying the matrix of transistor cells has first portions (201) that contact one the drain metal strips with first and second vias (79) and second portions (101) that contact one of the source metal strips with third and fourth vias (78).

Abstract: In one embodiment, a bipolar cell (31) includes a cell boundary (32) that defines a cell active area (33), a first array of bipolar transistors (41) is formed within the cell active area (33) and configured for a first function. The bipolar transistors (42) within the first array (41) are parallel to each other. The bipolar cell (31) further includes a second array of bipolar transistors (61) formed within the cell active area (33) and configured for a second function that is different than the first function. The bipolar transistors (62) within the second array (61) are parallel to each other and oriented in a different direction than the transistors (42) in the first array (41).

Abstract: A method for forming a direct chip attach (DCA) device (1) includes attaching a chip (3) to a lead frame (2). Conductive studs (22) are attached to bonding pads (13) on the chip (3) and a flag (18) on lead frame (2). The chip (3) and flag (18) are enclosed with an encapsulating layer (4), and openings (6) are formed in an upper surface (7) to expose conductive studs (22). In one embodiment, a masking layer (51) is applied to the lead frame (2), and the structure is then placed in an electroless plating apparatus (61). While in the plating apparatus (61), an injection device (66) injects plating solution (71) towards the upper surface (7) and openings (6) to enhance the formation of barrier layers (24) on the conductive studs (22). Solder bumps (9) are then attached to barrier layers (24) through the openings (6).

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84, 85, 87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: An apparatus for rapid thermal processing is described and includes a cylindrical lamp array structure (13) surrounding a cylindrical process tube (16). The cylindrical process tube (16) has a lengthwise central axis (22). The cylindrical lamp array structure (13) includes heat sources or lamps (26). The lamps (26) are positioned with respect to the cylindrical process tube (16) so that the sides of the lamps (26) focus light energy in the direction of the lengthwise central axis (22). Substrates (12) are oriented within the cylindrical process tube (16) so that the major surfaces (14) of the substrates (12) are substantially normal to the lengthwise central axis (22). In an alternative embodiment, a magnetic field source (19) is included for processing storage devices such as non-volatile memory devices.

Abstract: An apparatus for rapid thermal processing is described and includes a cylindrical lamp array structure (13) surrounding a cylindrical process tube (16). The cylindrical process tube (16) has a lengthwise central axis (22). The cylindrical lamp array structure (13) includes heat sources or lamps (26). The lamps (26) are positioned with respect to the cylindrical process tube (16) so that the sides of the lamps (26) focus light energy in the direction of the lengthwise central axis (22). Substrates (12) are oriented within the cylindrical process tube (16) so that the major surfaces (14) of the substrates (12) are substantially normal to the lengthwise central axis (22). In an alternative embodiment, a magnetic field source (19) is included for processing storage devices such as non-volatile memory devices.

Abstract: In one embodiment, a polishing apparatus (10) includes a retaining ring (12), a pressure ring (16), a first seal (18), and a second seal (20). The retaining ring (12) is movably attached to the pressure ring (16) to create a uniform pressure distribution across the retaining ring (12). In addition a positive fluid pressure is applied to the first seal (18) and the second seal (20) to create the uniform pressure distribution across the retaining ring (12). The uniform pressure distribution across the retaining ring (16) allows a semiconductor substrate (51), polished with the polishing apparatus (10), to have a reduced edge exclusion, and thus increased die yield.

Abstract: A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.

Abstract: An apparatus for probing high frequency electronic devices in wafer form comprising a high frequency wafer probe (16,56) having a conductor (36,61), a dielectric layer (37,71,72), a grounding layer (38,81,82,91), a signal probe needle (39,86), and a pair of ground needles (43,72,76) coupled to a substrate (11,51). A plurality of high frequency wafer probes (16,56) can be coupled to the substrate (11,51) to probe high density high frequency electronic devices and to probe high frequency electronic devices having varying bonding pad layouts. The high frequency wafer probe (16,56) is less sensitive to varying bonding pad height. The apparatus is suitable for probing high frequency electronic devices in a wafer manufacturing environment.

Abstract: A chemical mechanical planarization tool that reduces a volume of polishing chemistry used in a wafer polishing process includes a rinse bar (87) for removing polishing chemistry and particulates from a polishing media and a slurry measurement system (84) for regulating a pump (83) of a slurry delivery system. A volume of the slurry delivery system is reduced to less than 100 milliliters. Approximately a minimum volume of polishing chemistry for polishing a single wafer is dispensed during each wafer polishing process of a wafer lot. During each wafer polishing process the slurry delivery system is purged to prevent settling, agglomeration, and hardening of the polishing chemistry. The rinse bar (87) sprays a surface of the polishing media to remove spent polishing chemistry and particulates prior to polishing another semiconductor wafer.

Abstract: A single crystal ingot (10) is grown by first inserting a single crystal seed (14) into a melt (11) and pulling the seed (14) at a high pulling rate to grow a single crystal neck (15). The pulling rate is then altered to grow an overhang (18) with a diameter greater than that of the single crystal neck (15). An elongated body (19) is formed below the overhang (18) by adjusting the pulling rate. A multi-arm fixture (30) grabs the overhang (18) to alleviate the tensile and torsional stresses in the single crystal neck (15) that may be caused by the weight and the rotational motion of the single crystal ingot (10).

Abstract: A method for forming a relaxed semiconductor layer (12) includes forming a strained semiconductor layer on a substrate (11). The strained semiconductor layer has a different lattice constant than the substrate (11). Without exposing the strained semiconductor layer to an oxidizing ambient, the strained semiconductor layer is relaxed using thermal stress.

Abstract: A media compatible microsensor structure (11) for sensing an environmental condition in a harsh media includes an inorganic protective film (17) covering portions of the structure that will be exposed to the harsh media. In one embodiment, the microsensor structure (11) includes a microsensor package (12), a microsensor device (16) bonded to the microsensor package (12), a leadframe (13), a connective wire (14) connecting the microsensor device (16) to the leadframe (13), and an inorganic protective film (17) formed on all or portion of the exposed surfaces of the structure.

Abstract: An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

Abstract: An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Abstract: A three dimensional packaging approach reduces the overall footprint for interconnecting multiple semiconductor die. An three-dimensional folded module (10) produces a final package having a footprint size reduced by an approximate factor of four when compared to conventional electronic packaging. The module has a protective covering such as a cap (62) or a sealant (64) as a moisture barrier. Thus, high integration using flexible appendages (15, 25, 35, and 45) attached to a rigid substrate (12) and singularly folded above the substrate (12) results in both a small footprint package and also a light package. A reel-to-reel flex tape (56) assembly provides pre-tested flex boards (16, 26, 36, and 46) resulting in a cost-effective manufacturable package for semiconductor components.