Abstract: The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors.

Abstract: An on-screen display processor for a digital video signal processing system is disclosed. The OSD processor includes logic for converting a graphics bitmap in 4:4:4 format to graphics image words in 4:2:2 format for blending with video image words in a blend multiplexer of the digital video decode system. The OSD processor provides the graphics image words with blended chrominance values each obtained by merging chrominance values of at least two adjacent picture elements of the graphics bitmap. The merging includes mathematically combining U chrominance values of the at least two adjacent picture elements to produce a blended U chrominance and mathematically combining the V chrominance values of the at least two picture elements to obtain a blended V chrominance. In one embodiment, the mathematically combining comprises averaging the U chrominance values to obtain the blended U chrominance and averaging the V chrominance values to obtain the blended V chrominance.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.

Abstract: Impingement plate and jet nozzle assemblies are presented for use in cooling an electronic module. The assemblies include a thermally conductive plate having a first main surface and a second main surface with a plurality of concave surface portions formed in the second main surface extending towards the first main surface. Each concave surface portion has a conic section profile. A plurality of jet nozzles are disposed above the thermally conductive plate with each jet nozzle being aligned over a respective concave surface portion, wherein fluid introduced into a concave surface portion through the respective jet it nozzle impinges upon a lower portion thereof and flows outward along the concave surface portion. Each conic section profile is one of an elliptical section, a circular section, or a parabolic section.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A method in which a separate preformed optical material is suitably sized for easy handling, manipulation, and fabrication into a waveguide having a core (formed from the optical material) having transverse cross-sectional dimensions on the order of only tens of microns. The method may include a plurality of mechanical steps, e.g., lapping, polishing, and/or dicing, and bonding steps, e.g., attaching with adhesives. In one embodiment, the method includes the steps of providing an optical material, thinning and polishing the optical material to form a core comprising a plurality of longitudinally extending surfaces, providing a plurality of support substrates, and attaching the plurality of support substrates to the longitudinally extending surfaces of the core. The plurality of support substrates may be attached to the plurality of longitudinally extending surfaces of the optical material with an adhesive.

Abstract: A Dynamic Multicast Routing (DMR) facility is provided for a distributed computing environment having a plurality of networks of computing nodes. The DMR facility automatically creates virtual interfaces between selected computing nodes of the networks to ensure multicast message reachability to all functional computing nodes within the distributed computing environment. The DMR facility employs a group of group leader nodes (GL_group) among which virtual interfaces for multicast messaging are established. Upon failure of one of the group leader nodes, another computing node of the respective network having the failing group leader node is assigned group leader status for re-establishing virtual interfaces. Virtual interfaces are established between the group leader nodes such that redundancy in message routing is avoided.

Abstract: A semiconductor device, full bridge converter employing the same, and methods of fabrication thereof are provided. The device includes a vertical MOSFET having a parasitic body diode at a junction face between a body region and a semiconductor layer thereof. The parasitic body diode is suppressed by having no direct electrical connection to the body region, resulting in the parasitic body diode being open-circuited within the MOSFET. Co-packaged with the MOSFET is a separate bypass diode connected across a source and a drain of the MOSFET. The bypass diode functions to clamp the voltage across the MOSFET without employing the parasitic, electrically isolated body diode of the MOSFET.

Abstract: An electronic module is provided having an integrated thermoelectric cooling assembly disposed therein coupled to the module's electronic device. The thermoelectric assembly includes one or more thermoelectric stages and a thermal space transformer, for example, disposed between a first thermoelectric stage and a second thermoelectric stage. The electronic device is mounted to a substrate with the thermoelectric assembly disposed in thermal contact with the electronic device and a thermally conductive cap is positioned over the thermoelectric assembly, and is also in thermal contact with the thermoelectric assembly. Power to the thermoelectric assembly can be provided using electrically conductive springs disposed between one or more stages of the assembly and pads on an upper surface of the substrate, which electrically connect to power planes disposed within the substrate.

Abstract: A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: Controllable fiber optic attenuators and attenuation systems are disclosed for controllably extracting optical energy from a fiber optic, and therefore attenuating the optical signal being transmitted through the fiber optic. A portion of the fiber optic is etched or tapered, thereby providing a side surface through which optical energy can be extracted. The portion of the fiber is suspended between two support points, and a controllable material is formed over the surface for controllably extracting optical energy according to a changeable stimulus applied thereto, which affects the refractive index thereof. In one embodiment, the changeable stimulus is temperature, and a controllable heating/cooling source can be provided in the attenuator for control of the attenuation. The limited amount of thermal contact between the suspended portion of the fiber optic and the controllable material to surrounding structures offers a more predictable response, and improved response time.

Abstract: A capping structure and capping method are presented for an electronics package having a substrate and one or more electronics devices disposed on the substrate. The capping structure includes a capping plate sized to cover the electronics device(s) disposed on the substrate, and two or more force transfer pins. The force transfer pins are disposed between the capping plate and the substrate so that when a force is applied to the capping plate or the substrate, the force is transferred therebetween via the force transfer pins. Various capping plate and pin configurations are presented.

Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Abstract: A priority encoding technique is provided which outputs a code corresponding to the highest-priority input line among input lines having a true value when true values are input to more than one of the input lines, which are prioritized and given codes. The technique includes performing higher-order-bit encoding by outputting higher-order bits corresponding to the group having its highest priority among those groups distinguished by the higher-order bits to which true values are input; and performing lower-order-bit encoding to output lower-order bits corresponding to the input line having the highest priority among input lines to which the true values are input. Further, the lower-order-bit encoding includes invalidating the input of true values into the input lines to groups having lower priorities than the highest-priority group distinguished by the higher-order bits.

Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Abstract: An object of the present invention is to inform a person who adjusts the direction of an antenna 70 of the intensity of a signal received by the antenna 70 without connecting or adding special equipment to the antenna 70 or a connection cable 74. The satellite receiver 20 comprises: a received intensity information outputting means 22 for outputting received intensity information describing the intensity of a signal received from the antenna 70; a modulating means 30 for superimposing the received intensity information on a carrier wave; and a superimposing means 40 for superimposing the carrier wave carrying the received intensity information on a connection cable 74.