Abstract: A container with a freezable liquid for use in or out of an ice chest for temporary cooling purposes. The container of the invention is generally to have a top and a bottom and four sides connected to form a rectangular box type structure. The sides are to have dovetail joints that work as a fastening means to connect more than one together, thus making for a longer lasting cooling means. The invention can also be made without dovetail joints in groups of one or more. These groups would also have a long lasting cooling effect as they would work similar to a block of water-ice. The container of the invention is to have a cylindrical opening in the top that rescinds down toward the bottom, said opening is to be about the size of a pop can. This cylindrical opening is the heart of the invention as it allows a cooling effect from around the periphery as well as the bottom.

Abstract: A printer is provided with a band 44 attached to the printhead 54 to move to-and-fro across the line of printing, and around rollers (98,110) allowing it to pass beneath a printing support bed 12 so that introduced documents and documents being printed are restrained from excessive separation from the printing support bed 12. The band 44 is supported in association with the printhead 54 by non-return cylinders 58,64 capable only of uni-directional rotation. Each cylinder 58,64 is provided with a rotary spring 76 which takes up any excess length developing in the band 44. Spring loaded rollers 98,110 at either end of the printing path support the band 44. Electrical indication is provided when one, the other or both of the cylinders 58,64 cease to take up excess length and when one, the other or both of the spring loaded rollers 98,110 also cease to take up excess length in the band 44.

Abstract: An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.

Abstract: An automatic ticket handling machine AT adapted for use as a ticket vending station, presenting a display screen D, a telephone receiver-speaker unit TEL and a credit card reader unit CR, etc.Within machine AT is a sheet handling mechanism adapted to receive processed tickets (from a printer) in a "holding bin" secured within the machine which can either "dump" them or be shifted to present them to a user automatically when the user raises the access door of machine AT.

Abstract: An apparatus and method are provided for automatically converting a bottom-up software representation of a logical circuit design, such as created by a computer aided design (CAD) system, into a behavioral software representation which can be simulated at relatively high speed.

Abstract: A wide deviation tracking filter is provided which has the input signal to be tracked applied to a low frequency phase-locked loop circuit which performs coarse filtering of the phase noise on the input signal. A digital phase shifter is connected in series in the low frequency phase-locked loop and produces a pair of quadrature clock signals which are at the frequency of the input signal and at half the frequency of the output of the voltage control oscillator of the low frequency phase-locked loop. The pair of quadrature signals are connected to an image reject circuit. The image reject circuit is connected in series in the loop of a high frequency phase-locked loop which operates at a much higher frequency than the low frequency phase-locked loop and performs the function of further filtering the phase noise on the input signal to provide an output signal having ultra-low phase noise.

Abstract: Apparatus and a method of generating very very long pseudonoise (PN) spread spectrum codes is provided where the code is so long that it need never repeat itself during actual use. The transmitter is adapted to start to transmit one set of a plurality of component codes as a composite code having correlation properties with the component codes. When the first set of component codes are acquired at the receiver the composite code is then transmitted as a component of a different composite code which contains the previous composite code and a second new set of component codes which have correlation properties with the new set of component codes. When the second set of component codes are acquired by the receiver the composite code is then transmitted as a third new and different composite code which contains a third new set of component codes which have correlation properties with third new set of component codes.

Abstract: A variable rate near perfect rectangular matched filter is provided with a low pass filter coupled to the input symbol data stream. The output of the filter is coupled to a sampler and the output of the sampler is coupled to an analog to digital converter to provide digital samples indicative of the data stream at a time occurring between input data symbols. The output of the analog to digital converter is applied to a digital adder which has a filter correction input factor to adjust the output of the digital adder so that the digital samples approximate very closely the output of a perfect rectangular matched filter.

Abstract: Disclosed is a servo control system for a disk drive actuator using a bi-directional (Up/Down) Difference Counter along with a control circuit therefor which signals the counter each time a "rest position" is passed, indicating whether this passage is toward, or away-from, the destination track.

Abstract: An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be written with new instruction data from a fetch module while a previously written page is concurrently being read by the execute module for execution of a designated data processing operation. When the execute module completes execution and requires a new block of data, the two pages are logically switched by toggling an address bit.

Abstract: Apparatus is provided for compressing unfocused synthetic aperture radar (SAR) phase history pixel data by coupling the complex inphase phase history data output from the SAR to a first converter/compressor which produces compressed scalar log amplitude data and scalar phase pixel data. The output from the first converter/compressor is applied to a series to parallel converting means for converting plural scaler pixel data into vector data representative of a plurality of pixels. The output of the series to parallel conversion means is coupled to a second converter/compressor for converting the plural scalar pixel data into compressed encoded data representative of a plurality of pixels of unfocused SAR phase history data which is transmitted as compressed unfocused phase history data.

Abstract: For a disk drive servo system using position and position-quadrature signals (P, Q), a method for automatically effecting "Absolute Track Registration" and compensating for "offsets" by using the peak position of one of signals (P or Q) to find "true" position (true offset) for the other (Q or P) wherein the R/W actuator is brought to rest at a reference position and sample-offset signal generated; while the corresponding magnitude of related positioning signals are detected--this being repeated until the peak values of said positioning signals is located whereupon the corresponding position-offset is derived as "true offset"--the actuator then being repositioned by this "true offset" value; and repeating this for a given number of track sites across the disk.

Abstract: Magnetic recording media wherein the record surface is coated with an isocyanate lubricant (and, preferably, a supercoat of like lubricant), such lubrication being adapted to inhibit spin-off and like depletion, despite frequent head-contact, while exhibiting good durability, wear resistance and recording characteristics over extended life (computer applications).

Abstract: A task control mechanism for maintaining a queue of ready or available processes linked together according to an assigned priority for a plurality of central processors where the processors may be assigned to the highest priority task when that processor is not busy executing some higher priority task. The task control mechanism also includes a mechanism for computing task priorities as new tasks are inserted into the queue or removed. The mechanism also maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: A method for measuring bit shift and other characteristics indicative of the performance of a magnetic storage system, particularly for a system employing a thin-film magnetic head. In a preferred embodiment, complementary patterns are written many times around a circular track of a magnetic disk, each pattern including relatively closely spaced magnetic transitions as well as relatively widely spaced magnetic transitions. The relatively widely spaced transitions are chosen so as to be substantially unaffected by any other transitions. Measurements are made with reference to these widely spaced transitions and averaged for the many patterns recorded in the track so as to rapidly provide highly reliable measurements indicative of system performance.

Abstract: Improved EMI/RFI shielding is provided for situations which require heavy duty wiping insertions, such as occurring when a relatively heavy electronic assembly is to be removably inserted in a cabinet. In accordance with the invention, inexpensive integral EMI/RFI strips of conductive spring material are riveted to opposite cabinet walls so as to be adjacent the wiping sides of the inserted electronic assembly. Each EMI/RFI strip contains integral longitudinally spaced projecting fingers formed to provide durable and highly reliable EMI/RFI shielding capable of withstanding many insertions and removals.

Abstract: An event allocation mechanism in a processing system which mechanism maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline.

Abstract: Apparatus for providing automatic clock de-skewing for a plurality of circuit boards of a data processing system. In a preferred embodiment, each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board. In a preferred implementation of the clock de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate reference delay are employed in conjunction with a phase comparator for automatically providing de-skewed clocks at the clock outputs of the clock distribution chip. The accurate reference delay is advantageously provided by a strip transmission line formed in a conductive layer of the multi-layer board containing the chips.

Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.