Patents Represented by Attorney Konrad Raynes Victor & Mann
  • Patent number: 6537906
    Abstract: Certain embodiments provide a method for fabricating a semiconductor device in which a conductive layer containing silicon can be etched in a predetermined shape without adversely affecting a gate insulating film. A method for fabricating a semiconductor device in accordance with the present invention includes forming an oxide film 24 on a p-type silicon substrate 10 and forming a polysilicon layer 26 on the oxide film 24. A stopper layer 28 is formed on the surface of the polysilicon layer 26 and an organic antireflection coating 30 is formed on the surface of the stopper layer 28. A resist layer R is formed on the surface of the organic antireflection coating 30. The method also includes etching the organic antireflection coating 30 using the resist layer R as a mask and etching the stopper layer 28. The polysilicon layer 26 is also etched in a predetermined pattern to form a gate electrode.
    Type: Grant
    Filed: November 11, 1999
    Date of Patent: March 25, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Katsumi Mori
  • Patent number: 6538660
    Abstract: Disclosed is a system, method, and program for displaying data. A program receives first input graphics commands from a first application program to display first output on a display monitor and second input graphics commands from a second application program to display second output on the display monitor. The second output is graphically blended with an overlapping portion of the first output. Output graphics commands are generated from the first and second input graphics commands to display the graphically blended second output superimposed over an overlapping portion of the first output and the first output non-overlapping with the second output. This allows the content of the secondary output to be displayed without affecting user operations with respect to the primary application window.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Joseph Celi, Jr., Michael R. Cooper, Joseph Kubik, Jonathan Mark Wagner
  • Patent number: 6537869
    Abstract: Embodiments include a semiconductor device and a method for manufacturing the same, which simplify the manufacturing steps and provide split gate type non-volatile memory transistors and other device elements mounted on the same chip. In one method, the step of forming the lower electrode of a capacitor 540 and the step of forming a floating gate 40 of a memory transistor 400 are conducted in different steps. As a result, characteristics of the floating gate 40 and characteristics of the lower electrode 54 can be independently optimized. On the other hand, the step of forming a control gate 36 of the memory transistor 400 and the step of forming an upper electrode 58 of the capacitor 540 are conducted in the same step. As a result, the manufacturing process is simplified.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: March 25, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Tomoyuki Furuhata
  • Patent number: 6531356
    Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: March 11, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Masahiro Hayashi
  • Patent number: 6529938
    Abstract: Disclosed is a system, method, and program for executing operations on a client computer transmitted from a server over a network. A server operation is received indicating actions to perform on the client. A determination is made as to whether the requested operation is permitted according to a set of rules. The requested operation is executed on the client if there is no rule that prohibits the requested operation. The server is then notified that the requested action completed or that the requested action was not executed because of at least one rule prohibiting execution of the operation.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Stephen Thomas Cochran, Michael R. McNally
  • Patent number: 6528414
    Abstract: Embodiments include a manufacturing method for a semiconductor device which can suppress a concave from being generated in an upper area of a wiring layer at a position above plug. The method may include the steps of (a) forming an impurity diffusion layer 34; (b) forming, on the impurity diffusion layer 34, an interlayer insulating layer 40 having at least one. through hole 42; (c) forming a plug 50 in the through hole 42; (d) forming an underlying layer 62 on the plug 50 and the interlayer insulating layer 40, and (e) forming an aluminum layer 64 on the underlying layer 62, the aluminum layer 64 being formed at a substrate temperature not lower than 250° C. and under a reduced pressure.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: March 4, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yoshikazu Kasuya
  • Patent number: 6528897
    Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: March 4, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6526419
    Abstract: Disclosed is a method, system, program, and data structure for providing a shadow copy of data storage areas in a primary site to data storage areas in a secondary site. A definition is made of storage areas in the primary site having data to be shadowed and corresponding storage areas in the secondary site to shadow data at the storage areas in the primary site. A shadow pair comprises one primary storage area and one secondary storage area that shadows data for the primary storage area in the pair. A standard data transfer interface protocol command, such as a SCSI or Fibre Channel command, is used to configure status storage areas in the secondary site to provide status information and data for each primary and secondary storage area. A write command in the standard data transfer interface protocol is then used to write status information to the status storage areas indicating status of the shadowed data at the secondary storage areas in the pairs.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: February 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: David Alan Burton, Robert Louis Morton, Erez Webman
  • Patent number: 6522587
    Abstract: Embodiments relate to a non-volatile semiconductor memory device in which the interface state between the tunnel insulation layer and the floating gate and the interface state between the tunnel insulation layer and the control gate are lower, the operation characteristics are stable, and the data writing/erasing cycle life is long. A non-volatile semiconductor memory device (memory transistor) 400 may include a non-volatile semiconductor memory device with a split-gate structure having a source 16, a drain 14, a gate insulation layer 26, a floating gate 40, an intermediate insulation layer 50 that functions as a tunnel insulation layer, and a control gate 36. The intermediate insulation layer 50 is composed of at least three insulation layers 50a, 50b and 50c. The first and the second outermost layers 50a and 50c of the three insulation layers respectively contact the floating gate 40 and the control gate 36, and are composed of silicon oxide layers that are formed by a thermal oxidation method.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: February 18, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Furuhata, Atsushi Yamazaki
  • Patent number: 6522495
    Abstract: In summary, preferred embodiments disclose a system, method, and program for determining a value for non-mechanical noise within a disk drive system. The non-mechanical noise is likely related to instability in a head which reads data from a magnetic surface within the disk drive system. First, a sample of position error signals (PES) indicating non-repeatable runouts (NRRO) is provided from read operations within the disk drive system. Spectral analysis is then performed on the provided samples to calculate non-filtered power values for the NRRO values at different frequencies. A filtered power spectrum is determined within a frequency range excluding mechanical noise. A filtered power value is calculated from the determined filtered power spectrum within the frequency range excluding mechanical noise.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bernd Lamberts, Mantle Man-Hon Yu
  • Patent number: 6516634
    Abstract: Embodiments include a method for forming a glass which displays visible cracking prior to failure when subjected to predetermined stress level that is greater than a predetermined minimum stress level and less than a failure stress level. The method includes determining a critical flaw size in the glass and introducing a residual stress profile to the glass so that a plurality of visible cracks are formed prior to failure when the glass is subjected to a stress that is greater than the minimum stress level and lower than the critical stress. One method for forming the residual stress profile includes performing a first ion exchange so that a first plurality of ions of a first element in the glass are exchanged with a second plurality of ions of a second element that have a larger volume than the first ions. A second ion exchange is also performed so that a plurality of the second ions in the glass are exchanged back to ions of the first element.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: February 11, 2003
    Assignee: The Penn State Research Foundation
    Inventors: David J. Green, Vincenzo M. Sglavo, Rajan Tandon
  • Patent number: 6515756
    Abstract: Provided is a system for processing print jobs in which uniformity in print attributes across different servers and physical printers is maintained. One of a plurality of transform process is selected from at least two controllers to process input data files associated with print jobs. The controller including the selected transform process processes at least one configuration file to determine a set of print attribute values and submits the determined set of print attribute values to the selected transform process. The selected transform process processes the input data file in accordance with the submitted set of print attribute values to produce an output data stream. Additional transform processes executed in the controllers are selected. The controllers including the additional transform processing process the configuration file to determine print attribute values and submit the determined set of print attribute values to the additional selected transform processes.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: February 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Scott David Mastie, Arthur Ray Roberts
  • Patent number: 6514390
    Abstract: A magnetic shield to reduce sputtering of an RF coil for a plasma chamber in a semiconductor fabrication system is provided. The magnetic shield also reduces deposition of material onto the coil which in turn leads to a reduction in particulate matter shed by the coil onto the workpiece.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: February 4, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Zheng Xu, Fusen Chen, Jaim Nulman
  • Patent number: 6513097
    Abstract: Disclosed is a system and method for caching data. A processor receives data from a host to modify a track in a first storage device. The processor stores a copy of the modified data in a cache and indicates in a second storage device the tracks for which there is modified data in cache. During data recovery operations, the processor processes the second storage device and data therein to determine the tracks for which there was modified data in cache. The processor then marks the determined tracks as failed to prevent data at the determined tracks in the first storage device from being returned in response to a read request until the failure is resolved. In further embodiments, in response to detecting a partial failure within the storage system, the processor would scan the cache to determine tracks for which there is modified data stored in the cache.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: January 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Brent Cameron Beardsley, Michael Thomas Benhase, Robert Louis Morton, Kenneth Wayne Todd
  • Patent number: 6513028
    Abstract: Disclosed is a system, method, and program for searching a list of entries. Each entry is comprised of multiple fields. Each field in the entry may include one of a range of possible values for that field. If search criteria is provided for less than all of the fields, then multiple search keys will be generated such that each generated search key includes a search value for each field. The search value for each field for which there are no provided search criteria comprises one of the possible values for that field. A search operation is executed for each of the generated search keys to determine entries in the list that include field values that match the search values in the search key.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: January 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Christina Marie Lee, Lee-Chin Hsu Liu, Desai Paramesh Sampatrai, Hong Sang Tie, Shyh-Yee Wang, Yun Wang
  • Patent number: 6510050
    Abstract: A substrate for packaging a storage or server system may include one or more sections of the substrate configured to hold a two-dimensional array of disk drives. Another section of this substrate may be configured to hold circuitry for accessing the array of disk drives. This circuitry may include one or more processors. The substrate also includes a first plurality of ribs positioned in the first access of the substrate. The first plurality of ribs separate the sections from one another. The section configured to hold the control circuitry may also be configured to hold one or more power supplies for supplying power to the array of disk drives and control circuitry. This section, as well as other sections, may be divided in two by one or more additional ribs in a transverse direction. The substrate may be configured to be mounted in a cage or rack and may include an edge connector at one edge of the substrate to provide electrical connectivity to a back plane in the cage or rack.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: January 21, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Whay S. Lee, Nisha Talagala, Chia Y. Wu, Fay Chong, Jr., Randall D. Rettberg
  • Patent number: 6507948
    Abstract: Disclosed is a system, method, and program for creating a file, such as a batch file, that is capable of executing on one of many different operating systems. An object is processed including a plurality of instructions. Each instruction is associated with at least one executable function. A determination is made of an operating system in which the generated file will be executed. For each instruction in the object, a native operating system command is generated that is capable of executing the function associated with the instruction on the determined operating system. Each generated native operating system command is inserted into the file. Execution of the file on the determined operating system will execute the native operating system commands in the file to perform the functions associated with the instructions included in the object.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bryce Allen Curtis, Jimmy Ming-Der Hsu
  • Patent number: 6506693
    Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 14, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Roger V. Heyder, Thomas B. Brezocsky, Robert E. Davenport
  • Patent number: 6506287
    Abstract: A coil for inductively coupling RF energy to a plasma in a substrate processing chamber has adjacent spaced and overlapping ends to improve uniformity of processing of the substrate.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: January 14, 2003
    Assignee: Applied Materials, Inc.
    Inventor: Peijun Ding
  • Patent number: 6502157
    Abstract: Disclosed is a bridge system and method for prefetching data to return to a read request from an agent. The bridge system includes at least one memory device including a counter indicating a number of prefetch operations to perform to prefetch all the requested data, a first buffer capable of storing prefetch requests, and a second buffer capable of storing read data. Control logic implemented in the bridge system includes means for queuing at least one prefetch operation in the first buffer while the counter is greater than zero. The control logic then executes a queued prefetch operation, subsequently receives the prefetched data, and stores the prefetched data in the second buffer. The stored prefetched data is returned to the requesting agent.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventors: Gary William Batchelor, Carl Evan Jones, Forrest Lee Wade