Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A spin on insulating coating with ionic barrier properties is formed on a substrate, by mixing a P or B containing material such as phosphazene or borazine with a solution of silsesquioxane, spin coating on a substrate to form a film of pre-determined thickness. The coated film is cured in a step wise manner to drive out the solvents and most of the H and OH groups, with the resulting film having a composition SiONX, where X can be B, P, F and mixtures thereof. The amount of P, B or other elements are predetermined by calculating the solids in the silsesquioxane and adding suitable amount of borazine or phosphazene. The coated and cured film fills and planarizes any topography on the substrate created by etching trenches, forming gate stacks or metal lines. In one of the variation, the substrate has a layer of insulating material disposed thereon prior to the application of the spin-on insulator.

Abstract: A method of making electrical contacts to device regions in a substrate is taught. A first set of contacts are self-aligning and borderless and a second set of contacts are bordered. The method comprises the steps of providing a first insulating layer over the substrate and forming the first set of contacts in a self-aligned and borderless manner. This is followed by forming a second insulating layer over said first insulating layer, in which the second set of contacts that are bordered to the gate electrode and peripheral diffusions are formed through the first and second insulating layers. In addition, bordered contacts to the first set of borderless contacts are formed through the second insulating layer.

Abstract: A method of measuring bias of a minimum feature in a lithographic process uses creating an array of elements having a width and space corresponding to the minimum feature, and a length. The length change of the array element resulting from image shortening effect from a lithographic process is measured and the bias of the element in the width dimension is calculated. A test site having groups of array elements is described which facilitate automatic bias measurement of array lengths and separations and especially allows the use of non SEM metrology tools which is otherwise incapable of measuring the minimum feature width being monitored. Measurements by this method and test site used to control lithographic processing of substrates in manufacturing, routine monitoring of product substrates and lithographic tool and process for minimum bias, are disclosed.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: A method of forming a SOI device layer on an oxide layer on top of a substrate is disclosed. The process involves using a device substrate of a first conductivity having a top device layer of a second conductivity. Optionally, a thin layer of silicon dioxide is formed on top of the device layer. A carrier substrate is selected with a surface layer of silicon dioxide. Patterns are etched into the device and carrier substrates to preselected depths and surface widths, in a roughly complementary manner. The etched surfaces present a slope which enables the easy assembly of the device substrate and carrier substrate, the depths of the complementary patterns are controlled by the dopant layer thickness, and the slopes of etched profile are determined by the crystallographic orientations of the silicon substrate. The device substrate is thinned away to leave the device layer over the carrier substrate, thereby forming a device layer on the carrier substrate, separated by a silicon dioxide layer.

Abstract: A SRAM cell with cross-coupled transistors, a pair of transfer gate transistors and a pair of load resistors is manufactured by forming a plurality of field effect transistors in a silicon substrate. In one embodiment, the transistors are formed in an SOI substrate to improve soft-error resistance. An insulator layer is deposited over the source, drain and gate contacts (device contact areas), hole openings are etched into the insulating layer to expose a plurality of device contact areas. A highly resistive layer is patterned to substantially cover and in contact with some selected contact hole openings and device contact areas. A conductive material is deposited into all of the contact hole openings so as to substantially over-fill the contact hole openings and make electrical contact with the device contacts and patterned resistive layer.

Abstract: A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

Abstract: A structure for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.

Abstract: A method of measuring bias of a minimum feature in a lithographic process uses creating an array of elements having a width and space corresponding to the minimum feature, and a length. The length change of the array element resulting from image shortening effect from a lithographic process is measured and the bias of the element in the width dimension is calculated. A test site having groups of array elements is described which facilitate automatic bias measurement of array lengths and separations and especially allows the use of non SEM metrology tools which is otherwise incapable of measuring the minimum feature width being monitored. Measurements by this method and test site used to control lithographic processing of substrates in manufacturing, routine monitoring of product substrates and lithographic tool and process for minimum bias, are disclosed.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.

Abstract: A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode.

Abstract: A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

Abstract: A process, compatible with bipolar and CMOS processes, for making local interconnection of adjacent devices on a semiconductor substrate is disclosed. An electrically insulating etch stop layer is deposited over the semiconductor substrate including the device contact openings. A conductive layer is deposited over the etch stop layer. The conductive layer is patterned into a local interconnect by use of resist patterning and subtractive etching, stopping on the etch stop layer. By thermal activation, the conductive pattern and the underlying insulating material interact to become a single electrically conductive layer. This layer also establishes electrical contact to the devices thus completing the formation of the local interconnection of the devices on a semiconductor substrate.

Abstract: A process for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.

Abstract: A pick correlation method, comprises the steps of displaying a pick marker on a display screen; directing the pick marker at an image on the display screen, the image comprising at least one line primitive, and the pick marker having a pick window corresponding thereto; subjecting the at least one line primitive to a trivial test, whereby the at least one line primitive can be trivially tested by the trivial test if the at least one line primitive has both of its end-points outside of the same extended edge of the rectangular shaped pick window and, if successfully tested by the trivial test, accepting or rejecting the at least one line primitive in accordance with the results of the trivial test; and if the at least one line primitive cannot be trivially tested, subjecting the at least one line primitive to a non-trivial test which does not require performing floating point operations, and accepting or rejecting the at least one line primitive in accordance with the results of the non-trivial test.

Abstract: A method of pick correlation comprises the steps of displaying a pick marker on a display screen; directing the pick marker at an image on the display screen, the image comprising at least one line primitive, and the pick marker having a diamond shaped pick window corresponding thereto; subjecting the line primitive to a trivial test, the trivial test comprising enclosing the diamond shaped pick window in a least enclosing rectangle, wherein the diamond shaped pick window and the rectangle have a common center point, and rejecting the line primitive if the line primitive has both of its end-points outside of the same extended edge of the rectangle; if the line primitive cannot be trivially tested, subjecting the line primitive to a non-trivial test which does not require performing floating point operations, and accepting or rejecting the line primitive in accordance with the results of the non-trivial test; and considering accepted line primitives as being selected for further processing.

Abstract: A system and method for designing a structure such as a circuit. First the sensitivity of a circuit performance function (sensitivity data set - SDS) to at least one physical parameter is determined. Then, an estimated distribution of the design function calculated by using the SDS and random parameter values. Subsequently, the parameters corresponding to the estimated distribution was used to accurately calculate the tail. The tail is compared to a predetermined design objectives. If the objectives are not met, the design is modified and the calculation steps repeated until the design objectives are met.