Patents Represented by Attorney Krishnendu Gupta
-
Patent number: 5613063Abstract: A memory monitoring system equips a computer program for monitoring its own memory accesses. The system employs special values, called "VALUEA" and "VALUEB," stored in the memory locations and a table of write tags, each preferably a single-bit flag corresponding to a different one of the memory's locations. If the write tag is not set for a particular memory location, VALUEA within that location indicates that it is unallocated, and VALUEB indicates that it is allocated and not initialized. The write tags can be set to indicate that the corresponding memory location contains written data. The program so equipped can monitor each memory access, including, e.g., allocation, write, read, and memory freeing operations, using the combination of the location contents and the write tag table to determine valid memory operations and to signal memory access violations. Counters can be provided to track the number of valid accesses of particular types and/or of valid accesses to particular locations.Type: GrantFiled: July 1, 1994Date of Patent: March 18, 1997Assignee: Digital Equipment CorporationInventors: Robert A. Eustace, Louis Monier
-
Patent number: 5608883Abstract: A SCSI adapter for interconnecting first and second SCSI buses includes a filter for preventing BUSY glitches from being passed from one bus to the other. The filter includes a shift register connected to NAND logic. The SCSI adapter also has a circuit for establishing a desired timing relationship between DATA signals received over the first bus and corresponding ACK or REQ signals also received over that bus that indicate whether the DATA signals are valid. The circuit includes a DATA latch responsive to a delayed version of the ACK or REQ signal received at a clock input thereof. The output of the latch and the corresponding delayed ACK or REQ are transmitted over the second bus.Type: GrantFiled: February 1, 1993Date of Patent: March 4, 1997Assignee: Digital Equipment CorporationInventors: Robert R. Kando, Paul L. Godin
-
Patent number: 5594889Abstract: A memory resource allocation look ahead system is implemented in event logger (14), operating in conjunction with one or more event sinks (18). When the event logger (14) is called, all information in the argument fist is copied into an event buffer maintained by the logger (14), and the buffer is placed at the input end of queue (44). The event sinks 18 contain a similar queue. In operation of the event logger 14, an evd.sub.-- get.sub.-- event routine is used to obtain event reports from the event queue (44). The evd.sub.-- get.sub.-- event routine includes a next.sub.-- size.sub.-- hint argument, giving the size of the event record that will be obtained with the next call to evd.sub.-- get.sub.-- event. The next.sub.-- size.sub.-- hint argument is used to allocate memory for the next call to evd.sub.-- get.sub.-- event.Type: GrantFiled: May 30, 1995Date of Patent: January 14, 1997Assignee: Digital Equipment CorporationInventors: William K. Colgate, Kelly C. Green
-
Patent number: 5498965Abstract: Method for determining the characteristic impedance of a transmission line on a printed wiring board using time domain reflectometry. The method involves selecting a driving point in time, selecting an undisturbed interval, measuring voltage at predetermined time intervals across the undisturbed interval, determining from the measured voltages a curve representative of such voltages, and determining the voltage on the representative curve at the driving point. The characteristic impedance of the transmission line under test, denoted by Z.sub.0, is obtained by using the "driving point" of the transmission line as the reference plane for the impedance measurements.Type: GrantFiled: December 15, 1993Date of Patent: March 12, 1996Assignee: Digital Equipment CorporationInventor: Richard I. Mellitz
-
Patent number: 5483423Abstract: This disclosure pertains to an apparatus and method of providing EMI shielding for an electrical component. The apparatus includes an elastomeric gasket, which is coated with a conductive jacket, and which is mounted on the backplane of a cabinet, the backplane providing EMI shielding. The cabinet is adapted for the insertion of a plurality of electrical components, such as disk drives, tape drives, and power supplies, which themselves are mounted in a rigid frame member. The frame member includes EMI shielding for the components on five of their six sides. The sixth side is unshielded, due to the fact that it contains the electrical connector used to connect the component to the backplane of the cabinet, when the frame member is inserted in the cabinet. With the frame member providing shielding on five sides, and the backplane providing shielding for the sixth side, the gasket serves the purpose of establishing an electrical seal between the frame member and the backplane of the cabinet.Type: GrantFiled: January 9, 1995Date of Patent: January 9, 1996Assignee: Digital Equipment CorporationInventors: Mark S. Lewis, Reuben M. Martinez, Ralph M. Tusler
-
Patent number: 5450407Abstract: A frame having a desired destination address written into the destination address field of the frame is transmitted onto a first communications system, the frame is received by the apparatus, the frame is transmitted by the apparatus onto a second communications system with a second destination address written into the destination address field of the second frame, and also the desired destination address is written into a predetermined field of the second frame along with an indicator. The indicator is capable if being interpreted by a receiving station to mean that the desired destination address is written into the predetermined field of the second frame.Type: GrantFiled: June 7, 1994Date of Patent: September 12, 1995Assignee: Digital Equipment Corp.Inventors: Radia J. Perlman, William R. Hawe
-
Patent number: 5434864Abstract: A method for connecting a first communications system with a second communications system is disclosed. A first frame is received at a first station. The first station is connected to both the first communication system and the second communication system. The first frame has a destination address field, and the destination address field contains a desired destination address. The first station forwards, in response to the desired destination address, the first frame onto the second communications system as a second frame, and the first station writes a second destination address into a destination address field of the second frame. The first station writes the desired destination address into a predetermined field of the second frame. The first station writes, an indicator into the second frame, the indicator is capable of being interpreted by a receiving station to mean that the desired destination address is written into the predetermined field of the second frame.Type: GrantFiled: November 12, 1993Date of Patent: July 18, 1995Assignee: Digital Equipment CorporationInventors: Radia J. Perlman, William R. Hawe
-
Patent number: 5410917Abstract: The present invention is a method and an apparatus for the precise quantitative measurement of the magnitude of force exerted at the points of contact on a high density electrical interconnect that quantitatively determines the magnitude of the force. The invention includes the steps of establishing a pressing relationship between a photoelastic material and the high density interconnect, coupling plane-polarized light into the photoelastic material stressed as a result of the pressing relationship with the high density interconnect, coupling of the polarized light being at 45 degrees with the direction of pressing, capturing an image of the fringe pattern of the plane polarized light exiting the stressed photoelastic material, the fringe pattern comprising of fringes wherein the number of fringes varies with the magnitude of the pressing force, and counting the number of fringes produced to determine the magnitude of force exerted on the photoelastic member.Type: GrantFiled: July 1, 1993Date of Patent: May 2, 1995Assignee: Digital Equipment CorporationInventors: Terri Giversen, Mark Stratton, Nile F. Hartman
-
Patent number: 5408641Abstract: A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.Type: GrantFiled: April 1, 1994Date of Patent: April 18, 1995Assignee: Digital Equipment CorporationInventors: Michael A. Gagliardo, John J. Lynch, James E. Tessari
-
Patent number: 5392219Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.Type: GrantFiled: July 6, 1993Date of Patent: February 21, 1995Assignee: Digital Equipment CorporationInventors: Stephen M. Birch, Gerard M. Gavrel, Zaffar I. Memon
-
Patent number: 5383096Abstract: An apparatus for increasing the number of electrical I/O ports on an existing computer system chassis, while maintaining the RF shield of the chassis and without changing the design of the existing chassis, by the use of an I/O expansion box. The I/O expansion box comprises a bottom and a cover. The bottom has a base plate with openings for cables from the computer chassis to pass therethrough and has lips at the openings. The lips extend outwardly away from the recess and are used to attach the base plate to the chassis at its I/O port openings. The cover has a top with openings therein for the attachment of electrical cable connectors that are attached to the cables from the computer chassis. The number of openings in the top of the cover are greater than the number of openings in the base plate of the bottom.Type: GrantFiled: May 3, 1993Date of Patent: January 17, 1995Assignee: Digital Equipment CorporationInventors: Matthew C. Benson, Laurence M. Mazzone
-
Patent number: 5349690Abstract: A method and apparatus for selecting a particular node from a plurality of nodes connected to a common bus to allow the node to use the bus. The nodes have a pre-determined priority. After initially enabling the nodes, the bus is monitored for a bus idle condition. It is then determined which of the nodes are enabled message nodes, which are enabled nodes that have a message to send on the bus. There is then arbitration between the enabled message nodes after the bus is in the bus idle condition for a first period of time, such that the enabled message node having the highest pre-determined priority among the enabled message nodes is disabled for arbitration purposes, and also at the same time selects a target and performs a transfer. This procedure is repeated until all the enabled message nodes have been disabled. Thereafter, all of the nodes on the bus are enabled when the bus is in the bus idle condition for a second period of time, which is longer than the first period of time.Type: GrantFiled: February 11, 1993Date of Patent: September 20, 1994Assignee: Digital Equipment CorporationInventors: Robert C. Frame, Fernando A. Zayas, Edward A. Gardner
-
Patent number: 5347215Abstract: A semiconductor chip test jig for testing a chip 10 with "gull-wing" leads 11 comprises a body 20 and a cover 30. The body 20 has sets of fins or combs 23 which engage with the leads 11 to locate the chip 10 in the horizontal plane; the cover 30 has a set of "knife-edge" lead supports 35 formed to match a trim and form jig in the region of the leads 11 from where they emerge from the encapsulation of the chip 10 to their first bends; and the body 20 has a set of spring-loaded pins 24 which contact the leads opposite the lead supports.Type: GrantFiled: June 18, 1992Date of Patent: September 13, 1994Assignee: Digital Equipment International Ltd.Inventors: Ross L. Armstrong, George A. Meiklejohn
-
Patent number: 5343337Abstract: Circuitry is provided that interconnects a plurality of MR heads on a substrate with control circuitry using a lesser number of interconnecting paths. This reduces the number of required substrate pins to which the interconnecting paths are connected. The reduced number of substrate pins is such that it enables manufacturing and processing techniques to accommodate an increased number of MR heads on a given substrate over that which would be possible with the prior art interconnecting techniques.Type: GrantFiled: September 17, 1992Date of Patent: August 30, 1994Assignee: Digital Equipment CorporationInventor: Joe K. Jurneke
-
Patent number: 5335337Abstract: A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.Type: GrantFiled: January 27, 1989Date of Patent: August 2, 1994Assignee: Digital Equipment CorporationInventors: Michael A. Gagliardo, John J. Lynch, James E. Tessari
-
Patent number: 5332487Abstract: A method of and an apparatus for the electroplating of material onto substrates, such as computer memory disks, by use of a plating cell comprising cathodes, anodes, passive shields, filters, an oscillation system and an electrical power supply. Anodes and magnets are attached to the inside side walls of the plating cell. The magnets have a coating of an electrically nonconducting material covering it. Shields, each having a filter attached to it, are also fixed to the inside side walls. A pallet, having openings for holding disk substrates during electroplating, is placed between the shields in the plating cell. The disk substrates function as cathodes during electrolytic plating. The anodes and cathodes when electrically energized results in deposition of desired material, having uniform thickness, across the entire surface area of the substrate.Type: GrantFiled: April 22, 1993Date of Patent: July 26, 1994Assignee: Digital Equipment CorporationInventors: David J. Young, Jr., Scott L. Randall, Scott D. Shaw, Andrew F. Wylde
-
Patent number: D391927Type: GrantFiled: May 13, 1997Date of Patent: March 10, 1998Assignee: Digital Equipment CorporationInventors: Robert T. Faranda, Bradford G. Chapin