Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

Abstract: A sequencer control for controlling the time sequencing of the energization of controlled elements includes a microprocessor unit. A large number of input lines and output lines are uniquely multiplexed into a relatively small number of I/O terminals on the microprocessor. The multiplexing, the sequencing and all of the delays are effectively controlled by the microprocessor.

Abstract: Apparatus for determination of direction using the curl-free magnetic vector potential field. The apparatus includes apparatus for generating a predominantly curl-free magnetic vector potential field with a predetermined vector field spatial orientation. The field receiving apparatus includes a detecting apparatus with observable properties that vary with magnitude and orientation of an applied curl-free magnetic vector potential field. The apparatus can specify a direction of the field generating apparatus. A periodically rotating vector field can specify a path toward the field generating apparatus. The curl-free magnetic vector potential field can be established in conducting and opaque materials which are not capable of transmitting normal electromagnetic radiation.

Abstract: The present invention relates to a power sequence device which comprises an element which generates a sequencing code which is capable of being decoded by actuators included in the various equipment cabinets. The sequencing code is initiated by a sensing element which indicates the input power has reached a stable threshold whereupon the various cabinets comprising the data processing system are turned on in a desired order. Upon loss of power, the sensing element generates a warning signal indicating an impending power loss thereby enabling the equipment to perform an orderly halt.

Abstract: A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal.

Abstract: An integrated circuit package in which integrated circuit (I.C.) chips having flexible beam leads, the inner lead bond sites of which are bonded to input/output (I/O) terminals on the active faces of the chips, are mounted active face down on a surface of a substrate. The surface of the substrate is provided with chip sites and outer lead (OL) pads associated with each chip site. A preform of a fiber glass web coated with a thermosetting plastic is positioned on each chip site between a chip site and the active face of the I.C. chip. The plastic material of the preforms encapsulates the active faces of the chips, including a portion of each of the leads proximate a chip, and secures each chip to its chip site. The outer lead bond sites of the leads are bonded to OL pads of the substrate with the exposed portions of the leads between the OL pads and the encapsulated portion being bent away from the substrate and under compression.

Abstract: Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication.

Abstract: An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor, each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled by the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated is handled by the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation.

Abstract: A transport system for transporting fixtures adapted to hold a workpiece sequentially from a fixture transferor station to a fixture transferee station. A fixture guide rail interconnects the two stations and is provided with a chain guide recess that extends from one station to the other. A continuous plastic timing chain cable is mounted on a plurality of sprockets so that the chain can be made to rotate. The sprockets are positioned so that the timing chain is positioned in the chain guide recess. Drive pins are mounted in selected ones of the links of the chain so that the pins will project from one side of the chain. The drive pins initially contact a fixture positioned in the transferee station and move each fixture, in turn, along the guide rails to the transferee station. A drive motor is connected to one of the sprockets to cause the sprocket to move the chain. The distance between drive pins is substantially constant and greater than the corresponding dimension of the fixtures being transported.

Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.Two, three state busses are employed. The first, three-state data bus is used to transmit memory data to the error detection and correction (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state data transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.

Abstract: Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Abstract: A system for transferring substantially identical fixtures, on each of which is mounted a workpiece, from a stack of said fixtures in a transferor magazine to a transferee magazine. Each of the magazines has substantially planar walls defining a prismatic interior space having a substantially rectangular cross-section and open top and bottom, or end, faces. The walls of the magazine are provided with spring catches for retaining in the storage space fixtures placed therein, with the catches defining that portion of the interior of the magazine constituting a fixture storage space. The transferor magazine is mounted on a transferor base, which is provided with a transferor station and apparatus for placing the catches of the transferor base in a condition so that fixtures in the storage space can descend into the transferor station. The transferee magazine is mounted on a transferee base which is provided with a transferee station.

Abstract: An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.

Abstract: This relates to a fiber optics communication link, wherein a single optical fiber carries data bi-directionally between two computers. The first computer is coupled by means of control logic to a first transmitter and a first receiver. The first transmitter and receiver are in turn coupled to a single optical fiber by means of a Y-coupler. A second computer is similarly coupled via control logic to a second transmitter and second receiver, which is in turn coupled to the single optical fiber by means of a second Y-coupler. To minimize problems due to reflections, each receiver is disabled when its corresponding transmitter is transmitting data.

Abstract: A long term response enhancement for a digital phase-locked loop is implemented to provide a relatively minor change in the phase of the output signal over a relatively long period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur between successive input signals, producing an output signal when the two numbers agree.

Abstract: An integrated circuit package in which an integrated circuit chip having flexible beam leads, the inner lead bonding sites of which are bonded to input and output terminals on the active face of the chip, is mounted active face down on the top surface of a substrate. The top surface of the substrate is provided with a chip pad on which the integrated circuit chip is mounted and outer lead pads. The back surface of the substrate has a heat sink pad which is positioned substantially opposite the chip pad. A plurality of thermal passages is formed through the substrate interconnecting the chip pad and the heat sink pad. A good thermally conductive material fills the passages. A preform comprising a segment of fiber glass web coated with a thermosetting and thermally conductive plastic is positioned on each chip pad between the chip pad and the active face of the integrated circuit chip.

Abstract: In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.

Abstract: A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage locations, the contents of the second multiplicity of storage locations adapted for addressing the first multiplicity of storage locations, a counter for addressing the second multiplicity of storage locations; and control logic for controlling the counter and entry and withdrawal of data signals in the first and second multiplicity of storage locations.

Abstract: A method and apparatus for process control of batch processes utilizing the steps of storing in a memory the actual measured values of the process variable and utilizing the memorized values for an estimative operation to determine the timing for supplying a manipulated variable to the process. Thus, the process control apparatus of the present invention commits to memory the actual measured values of the process variable, utilizes the memorized values for the estimative operation to determine the point of time for suspending the supply of the manipulated variable and the point of time for starting the regular constant value control and, based on the outcome of this estimative operation, effects the separation of the process control under the steady condition from the control under the transient condition. Such a control operation ensures that the control value is not increased beyond its limit and, at the same time, it permits the adjusting period to be reduced to the minimum.

Abstract: An apparatus and method for decoding input signals on four lines to produce an outgoing information stream of binary bits.