Abstract: The method of mounting on a substrate an integrated circuit (I.C.) chip having flexible beam leads bonded to input/output (I/O) terminals on the active face of the I.C. chip. The substrate has a chip pad and outer lead (OL) pads associated with the chip pad on a surface of the substrate. Preforms of a fiber glass web coated with a thermosetting plastic are cut to a size that substantially conforms to that of the chip pad. The substrate and the chip pad are heated to a first temperature which the preform will adhere to the chip site, the preform is placed on the chip pad, and the active face of the I.C. chip is pressed into the preform. The temperature of the substrate, preform and chip, are then raised to a second temperature higher than the first to partially cure the thermoplastic material and to encapsulate the active face of the I.C. chip and portions of the leads proximate the chip in the thermoplastic material of the preform. The I.C.

Abstract: A tape transport speed control uses a speed controller supplied with packing density or digital bits per inch of recording medium and data rate or digital bits per second to compute the speed of the tape which would conform to these selected parameters by the speed being equal to the data rate divided by the packing density. The speed controller uses a combination of digital and analog circuits to produce a reference signal and a speed select signal for the tape transport speed control operation using a comparison between the reference signal and a tachometer signal to control the tape transport about the basic selected tape speed.

Abstract: A collision avoidance apparatus having a voltage source producing a predetermined voltage level. A switching network within the collision avoidance apparatus is capable of alternately applying the predetermined voltage level to the communication medium and of applying the voltage level of the communication medium to a logic network. The logic network indicates if the predetermined voltage level and the voltage level of the communication medium are approximately equal.

Abstract: An apparatus and method for encoding information receiving a binary information stream. The apparatus actuates one of four outputs as determined by the last output actuated and the binary level of the binary bit received.

Abstract: A slowly varying bias signal is added to one input of a Wave Form Transition Sequence Detector, as more fully described in a related application cited herein, to provide a differential output therefrom which is directly proportional to the time between transitions occurring on two input wave forms. The slowly varying bias modulates the level of one input wave form, and thereby varies the time required for the Wave Form Transition Detector to detect a transition occuring thereon. By symmetrically varying the response time of the Wave Form Transition Sequence Detector to one input wave form in the neighborhood of the occurrence of a transition on the second input waveform, the average differential output of the Wave Form Transition Sequence Detector over a cycle of the slowly varying bias level will be proportional to the time between transitions occurring on the two input wave forms.

Abstract: Two switching elements are cross-coupled in the standard bistable multivibrator arrangement. Two additional switching elements are added: one each in parallel with one of the switching elements forming the bistable multivibrator. The two wave forms under study are applied to the control gate of each of the additional switching elements. When both wave forms are in one state, the two additional switching elements are switched ON, effectively inhibiting bistable multivibrator action. The first wave form to change state results in its associated switching element switching OFF, which releases the bistable multivibrator circuit to assume the corresponding stable state, which observed differentially across the switching element forming the bistable multivibrator, is indicative of the wave form to first undergo transition.

Abstract: A multiposition switch is connected to two input data buses which buses can apply binary digital signals of two operands to the switch at one time. An output data bus is also connected to the switch. Depending upon the position of the switch, bits from one or both of the operands as well as bits from other sources are applied by the switch to the output bus so that the format of the operand on the output bus has a predetermined relationship to the operands on the input buses.

Abstract: There is disclosed herein an apparatus for displaying data and communicating with another data processing device via a parallel port or over a long distance communications network via a full duplex modem, said computer terminal utilizing a microprocessor for programmed control of the terminal. The terminal is capable of displaying information on a standard black and white television set and utilizes a keyboard for entering information to be displayed or sent to the main data processing system. Limited graphics with sixty four graphics patterns are also available by using the microprocessor chip to scan the keyboard and communicate with the modem and parallel ports, and by utilizing a standard television set instead of a cathode ray tube, substantial material cost savings can be made in building the terminal which could be built for under $250 in parts in 1979.

Abstract: An Integrated Circuit Package in which integrated circuit (I.C.) chips having flexible beam leads, the inner lead bond sites of which are bonded to input/output (I/O) terminals on the active faces of the chips, are mounted active face down on a surface of a substrate. The surface of the substrate is provided with chip sites and outer lead (OL) pads associated with each chip site. A preform of a fiber glass web coated with a thermosetting plastic is positioned on each chip site between a chip site and the active face of the I.C. chip. The plastic material of the preforms encapsulates the active faces of the chips, including a portion of each of the leads proximate a chip, and secures each chip to its chip site. The outer lead bond sites of the leads are bonded to OL pads of the substrate with the exposed portions of the leads between the OL pads and the encapsulated portion being bent away from the substrate and under compression.

Abstract: A maximum frequency detector having a counter which counts through a certain number of counts unless an inhibit signal is received at a rate determined by the frequency of the clock pulse received. The inhibit signal is generated by a logic network to prevent the counter from producing an outgoing digital pulse of the digital pulse stream. The counter, the clock pulse generator and the logic network cooperate to have the frequencies of the incoming and outgoing digital pulses equal unless the incoming digital pulse stream has its frequency exceed the predetermined maximum frequency. In the event that the frequency of the incoming digital pulse stream exceeds the predetermined maximum frequency the frequency of the outgoing digital pulse stream is the certain predetermined maximum frequency.

Abstract: In a computer system, with a system interface unit (SIU) for controlling data transfers between a lower speed main memory and either a central processor unit (CPU) or a high-speed cache memory unit (CMU), a cache memory command buffer (CMCB) circuit allows the SIU and CMU to operate independently of each other and ensures that commands to the CMU and SIU are executed in proper sequence. The CMCB circuit includes a stack sequence control scheme with circuitry for storing read and write signals from the CPU into read and write buffers and for outputting these signals to the CMU and SIU without interrupting the operation of either unit. The sequence control circuit includes an address decision network, a stack memory containing buffer pointers which indicate where the CPU read/write signals are located in the buffers, and a plurality of pointer registers or binary counters which indicate where buffer pointers (for particular read/write operations by the CMU or SIU) are located in the stack memory.

Abstract: An apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuitry for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed here is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger bandwidth of optical fibers.

Abstract: An information communication system having several transceivers connected to a communication medium. Each transceiver connected to a collision avoidance apparatus which determines if another transceiver is preparing to transmit on the communication medium by applying a unique predetermined D.C. voltage level to the communication medium.

Abstract: An apparatus and method correcting data groups within a data stream to form a corrected data stream and providing for selecting between the data stream and the corrected data stream as desired.

Abstract: There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.

Abstract: A control apparatus for a switching regulator circuit having a voltage controlled oscillator responsive to any deviation of the output voltage of the switching regulator circuit from a predetermined reference voltage. The voltage controlled oscillator produces a digital pulse stream having a frequency which is varied by the voltage controlled oscillator in response to any deviation of the output voltage of the switching regulator circuit from the predetermined reference voltage. A recovery detector is connected to at least one of the reactors of the switching regulator circuit to ensure that the particular SCR associated with that reactor has fully recovered prior to the next actuation thereof. If the particular SCR has not recovered then the digital pulse which would be distributed to that SCR within the digital pulse stream is held.

Abstract: An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement is also disclosed for selective clearing of the cache in multiprocessor systems where data in a cache becomes obsolete by virtue of a change made to the corresponding data in main memory by another processor. The advantage of higher overall speed for CPU operations is achieved because of the higher hit ratio provided by the disclosed arrangement. In the preferred embodiment, the cache utilizes: a cache store for storing data; primary and duplicate directories for identifying the data stored in the cache; a full/empty array to mark the status of the storage locations; a least recently used array to indicate where incoming data should be stored; and a control means to orchestrate all these elements.

Abstract: There is disclosed herein an apparatus for use in automated testing of elements in data processing systems such as the central processing unit. The system is comprised of a microprocessor with associated firmware, RAM and peripheral communications devices. There are two communication interface ports for receiving commands and instructions from local and remote computer terminals or from data processing units programmed to cause the testing apparatus to perform predetermined sequences of tests. There is also a port for connection to a portable maintenance panel which can be held in the hand of a field engineer for controlling the testing apparatus. The system is designed to replace prior art maintenance panels used for debugging computer hardware.

Abstract: A switching regulator circuit for utilization with power supplies supplying a high DC output current including a plurality of control rectifiers and inductive reactors with sequential gating of the rectifiers at regular intervals for providing overlapped output current pulses from the reactors. An output circuit receives the rippled current comprised of the overlapped output current pulses for reducing the ripple therein. The output circuit includes a choke in series with the output which induces phase shift between the rippled current and the output current. A sensing winding associated with the choke eliminates the phase shift voltage for forming a feedback signal as an input to a control circuit. The control circuit utilizes the feedback signal to control the rate at which the rectifiers are gated sequentially.