Abstract: A transmitter for transmitting at least a first and a second main signal component is disclosed, having at least two input terminals for receiving the at least two input signals. The transmitter comprises multiplexer means for multiplexing the at least two input signals to a first input of matrixing means, and to an input of first bitrate reducing means. The first bitrate reducing means is for carrying out a data reduction step on the signal applied to its input and to supply a data reduced version to an output. Expansion means are present, having an input coupled to the first bitrate reducing means, for carrying out a data expansion on the data information applied to its input, so as to obtain a replica of the signal applied to the input of the bitrate reducing means at an output. Said output is coupled to a second input of the matrixing means. An output of the matrixing means is coupled to signal combination means via second bitrate reducing means.

Abstract: In a television receiver, to prevent interference between the magnetic field used for degaussing and the magnetic field of the vertical yoke, a switch is used for delaying turning on the vertical deflection circuit during degaussing.

Abstract: A load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. The load stage also includes a switch connected between the first node and the second node. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

Abstract: The invention relates to a transmission system comprising a synchronizer for forming a multiplex signal, comprising at least a device for conveying the multiplex signal, and a desynchronizer. The desynchronizer comprises at least a buffer store for buffering transport unit data contained in the signal, a write address generator for controlling the writing of the data in the buffer store, a control arrangement for forming a control signal for the write address generator from the signal, a read address generator for controlling the reading of the data from the buffer store, a difference circuit for forming difference values between the addresses of write and read address generators and a generating circuit for generating from the difference values a read clock signal applied to the read address generator.

Abstract: A circuit arrangement which is provided with an up-converter (3) which comprises at least an inductive device (31), a switch (32), and a capacitive device (34) which in the operational state is periodically charged with a charging current in dependence on periodic switching of the switch. The switch is switched to the conducting state periodically during a substantially constant time t.sub.on. The circuit arrangement is provided with detection circuitry (I) for direct detection of the charging current. As a result, a load current which has a sinusoidal shape by good approximation is drawn from a connected AC voltage supply source by the circuit arrangement.

Abstract: In a television transmission system comprising an analog video channel scrambled with a control word which is changed occasionally and a NICAM sound channel scrambled with a control word which is also changed occasionally, and different scrambling and modulation circuits having independent clocks for the sound and video signals, a single control word generator is used for the sound and video signals and when this control word is changed for the video signal (17), a bit or a specific group of bits is incorporated in the subsequent sound data packet (18) indicating that a new control word is available, but the new control word will only be used for a subsequent data packet (19).

Abstract: A differential amplifier comprises a Darlington differential pair (T.sub.1 /T.sub.3, T.sub.2 /T.sub.4) and a cross-coupled transistor pair (T.sub.5, T.sub.6) to increase the transconductance of the Darlington differential pair (T.sub.1 /T.sub.3, T.sub.2 /T.sub.4). The negative input impedance of the differential amplifier as a result of the presence of the cross-coupled differential pair (T.sub.5, T.sub.6) is compensated for at high frequencies and the gain of the differential amplifier is reduced by a compensation circuit with a capacitor (30) between the control electrodes of the transistors of the cross-coupled differential pair (T.sub.5, T.sub.6) and with resistors (26, 28) in series with the control electrodes of the transistors of the cross-coupled differential pair (T.sub.5, T.sub.6).

Abstract: The subject of the invention is a differential sampler circuit including a voltage/current converter (1) having two differential inputs (E1a, E1b) and two outputs (S1a, S1b). According to the invention, each of these outputs is linked via an input multiplexer module (2a) to two interposed track-and-hold modules (5a, 6a), in such a way that at any instant one of the track-and-hold modules (5a, 6a) operates in track mode whereas the other (6a, 5a) operates in hold mode. These two modules (5a, 6a) are linked to the output (S4a) of the sampler circuit via an output multiplexer module (7a). This structure makes it possible to double the sampling frequency without increasing the intrinsic speed of the circuit. Each track-and-hold module (5a, 6a) includes an input load (10a, 11a) linked in parallel with a capacitor (C18a, C19a), an output emitter-follower transistor (T20a, T21a), and a switching cell (5-6a). Thus, the high-frequency performance of the circuit is improved.

Abstract: A system for receiving and decoding digital signals in accordance with two image definition levels. The system includes a transmission channel decoding sub-assembly; a source decoding sub-assembly for decoding signals of a higher definition level or signals of a lower definition level; a device for displaying the decoded signals available at the output of this sub-assembly; at a second output of the sub-assembly, a device for detecting errors during source decoding, followed, in series, by a decision circuit for controlling the switch in accordance with the output signal of said error detection device, as well as for controlling the change-over of the decoding sub-assembly from one of the two source decoding modes to the other.

Abstract: Transmitter including a controllable power amplifier, whose output signal is fed back to a control input of the power amplifier via a detector device which produces a detector signal for detecting the output power of the power amplifier, and comprising a signal generator for producing a control signal which is used for forming the output signal and has rising and falling edges. A control signal is derived from the comparison of the detector signal with the reference value which control signal has a rising edge and thus also terminates the increase of the transmitted power. The transmitter is used in time-division multiplex systems, more specifically, in mobile and fixed stations in a mobile radio system according to the GSM standard.

Abstract: A line driver comprising: an input terminal for receiving an input signal, an output terminal for connecting a load, a first and a second transconductance-controlled transconductor having substantially equal transconductances, each transconductor having a non-inverting input, an inverting input, an output and a common control input for controlling the transconductance, the non-inverting inputs of the first and second transconductors being coupled to the input terminal, the outputs of the first and second transconductors being coupled to the output terminal, the inverting input of the first transconductor being coupled to a point of reference potential, the inverting input of the second transconductor being coupled to the output terminal, and an amplifier having a non-inverting input, an inverting input and an output coupled to, respectively, the input terminal, the output terminal and the common control input of the first and the second transconductors.

Abstract: A lighting system having an electric lamp controlled by an infrared remote controller. The remote controller incorporates a commercially available transmitter and receiver which reliably functions in the presence of infrared noise having frequencies at and about the carrier frequency of the transmitted signal. The remote controller receiver outputs a demodulated signal and a filter acts on the demodulated signal to remove noise present in the demodulated signal caused by the electric lamp by comparing measured time intervals between leading and trailing edges of the demodulated signal to predetermined values defining data elements.

Abstract: A method for tracking down a prespecified subcircuit in an electrical circuit equivalent is described. The subcircuit is prespecified by a template circuit comprising a pattern of interconnections between template elements in the template circuit and associated type conditions for each template element. The method comprises the steps of counting, for each associated type condition, a respective occurrence rate of circuit elements in the electrical circuit equivalent which meet the type condition, selecting an initial template element whose type condition corresponds to a lowest occurrence rate, and selecting an initial circuit element meeting the type condition for the initial template element. Subsequently in the electrical circuit equivalent a search is made for successive further circuit elements, coupled to the initial circuit element according to the pattern and satisfying the type conditions for the template elements, until either all template components are identified or persistent failure is met.

Abstract: Device for processing digital signals constituted by image blocks and hierarchically arranged types of data. This device comprises an addressable memory (40) for storing said signals, a circuit (10) for counting, per section, the number of bits corresponding in these signals to each type of data, a circuit (20) for assigning, to each of the image sections and in accordance with a given proportion, the number of bits to be transmitted in channels of different priorities, and at the output of said circuits a control circuit (30) for redistributing the bits for each of the sections and in packets of given lengths comprising at least the first bits of a block and possibly the leftover bits of the other blocks. The invention also relates to the device for inverse processing at the receiver end.

Abstract: A device for encoding digital signals corresponding to images which are subdivided into blocks has a first encoding channel including a discrete cosine transform circuit. In addition to this first encoding channel the device has a second encoding channel which encodes the differences between the original coefficients present at the output of the discrete cosine transform circuit and the same coefficients after quantization and inverse quantization. This second channel encodes the differences after they are quantized with a finer quantization step than in the first encoding channel. The device further includes a prediction channel including a motion compensation stage, that uses both the inverse quantized coefficients coded in the first encoding channel and the inverse quantized coefficients coded in the second encoding channel to produce a predicted digital signal. This predicted digital signal is subtracted from the digital signal to be encoded by the device.

Abstract: The invention provides an integrated amplifier whose gain factor is adjusted by means of an auxiliary amplifier . The gain factor is determined by the ratio of two on-chip resistors and by the ratio of the dimensions of transistors in long-tailed pair circuits in the signal amplifier to those of the transistors in the long-tailed pair circuit in the auxiliary amplifier. Both resistance ratios and ratios between complete circuits can be realised highly accurately in integrated circuits. As a result, the accuracy of the gain factor is great. In an embodiment of the invention the dimensions of the long-tailed pair circuits in the auxiliary amplifier and in the signal amplifier are the same. This achieves that if the adjusting voltages and adjusting currents of corresponding transistors in the long-tailed pair circuits are the same, the gain factor is over a large range independent of supply voltage and temperature.

Abstract: An amplifier arrangement comprises an inverting transconductance stage having an input and an output; a capacitor coupled between the input and the output of the inverting transconductance stage; and signal current means having a first output coupled to the input of the inverting transconductance stage to provide a first signal current to the input of the inverting transconductance stage. The signal current means further comprises a second output coupled to the output of the inverting transconductance stage to provide a second signal current to the output of the inverting transconductance stage, which second signal current is substantially equal and in phase opposition to the first signal current. A second parallel path bypasses the Miller-compensated transconductance stage to eliminate the right half-plane zero of the Miller compensation.

Abstract: An electrical machine comprises a stationary first section (1) and a second section (5) which is movable relative to the stationary section. At least one of the sections comprises a soft-magnetic part (7) and a hard-magnetic part (9). A surface (7a) of the soft-magnetic part and a surface (9a) of the hard-magnetic part are fixed intimately to one another by direct bonding.

Abstract: Matrix memories comprising row conductors and column conductors, at the intersections of which storage elements are arranged, are often tested by complete addressing of all elements. Different bit patterns are written into the memory and tested upon reading. However, when the elements arranged at the intersections are EEPROM storage cells, requiring a substantial amount of time for writing, the complete testing of the memory in this manner would be very time consuming. In accordance with the invention, therefore, only the addressing of the matrix is tested, use being made of a special test bus which can be connected to the row conductors and the column conductors via switches. As a result, not only the row conductors and column conductors themselves, but also the associated decoders and selection elements can be tested for correct operation.

Abstract: A first signal processor stage of an audio amplifier arrangement influences the signal strength of a received audio signal for at least part of the frequency range of the received audio signal. An output amplifier stage amplifies the audio signal influenced by the first signal processor stage. The audio amplifier arrangement further includes a transformer having a primary winding connectable to a mains voltage and having a secondary winding connected to an AC/DC converter whose outputs are connected to at least the output amplifier stage for feeding the output amplifier stage. A detection circuit generates a detection signal (Vms) which is related to the power load of the transformer. An analysis circuit detects in response to the detection signal whether the rise in temperature occurring in the transformer due to the power load has exceeded a specific norm.