Abstract: Instant replay is provided in the picture-in-picture portion of the television display without requiring compression and decompression techniques. A string of consecutive fields is received and decimated. A plurality of non-consecutive fields is selected and stored in DRAM. Fields are continuously stored until a user selects to view the last stored frames. The last stored frames are then replayed in the PIP portion of the television.

Abstract: A video decoder including a control unit (CC), a picture memory (P) and a loop filter (F) for blockwise decoding of coded video pictures (q). The blockwise decoding generally leads to artefacts in the display of the decoded video pictures on a monitor (M), which artefacts can be substantially suppressed by filters arranged downstream of the decoder. A similarly substantial suppression of the artefacts with a small extension of the number of components is characterized by means with which the control unit (CC) is enabled, in the decoding intervals,(a) to read predetermined pixel data of a decoded video picture from the picture memory (P) and to apply them to the loop filter (F) for the purpose of filtering,(b) to select the predetermined pixel data in such a way that the filtering operation is performed beyond the block edges of the blocks provided for decoding. The measures described are compatible with a decoder as defined in the H.261 Recommendation.

Abstract: A motor control arrangement including a control circuit for controlling the speed of an electric motor (EM), which control circuit comprises a measurement resistor (MR) and a switching transistor (ST) having a control electrode and a main current path coupled in series with the electric motor (EM) and the measurement resistor (MR), a pulse width control stage (PW) coupled to the control electrode of the switching transistor (ST), a motor current measurement stage (MI) for controlling the pulse width control stage (PW) in response to a motor current of the electric motor (EM), and a motor voltage measurement stage (MV) for controlling the pulse width control stage (PW) in response to a motor voltage (EM) of the electric motor (EM).

Abstract: A clocked comparator having an input differential amplifier, a sample and hold circuit, and a load stage. The load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

Abstract: In a method of reducing the noise in a signal from a motion detector for video signals, in which a part of the amplitude range of the signal below a threshold value is suppressed, the minimum of the signal is determined by means of a control loop, starting with a minimum threshold value. The threshold value is increased when the minimum of the signal exceeds a given value, preferably 0, and is reduced when the minimum of the signal lies below the given value.

Abstract: A description is given of a circuit arrangement for producing at least an output direct voltage (at 18, 19) from an at least significantly sinusoidal input a.c. voltage (at 2, 3) of a first frequency, comprising a first rectifier device (1), to which the input a.c.

Abstract: A device for encoding a video signal comprises a picture transformer (22), a quantizer (23) and a variable-length encoder (24), as well as distribution device (6) for distributing a global target value (T) for the number of bits per picture or group of pictures in local target values (T.sub.n) for separate macroblocks of each picture. The device for encoding is provided with proportionally integrating control device for for controlling the quantization step size (Q.sub.1) in such a way that the buffer contents (b) of an output buffer (4) are in conformity with the target value. Since the PI control circuit does not introduce any residual errors, the desired number of bits per picture or group of pictures is achieved within narrow limits. The output signal is eminently suitable for recording and subsequent editing.

Abstract: A communication system has multiple and uniformly weighted station interconnected by a shared digital bus. A particular station comprises globally relevant information, and, with a predetermined maximum recurrence time, transmits a data packet representing such item to any other interested station. If unanimous counter signalization occurs, the item is in order, other wise updating thereof is undertaken. The unanimity is either by positive signalization, or by default.

Abstract: A microprocessor includes a processor element, a memory interface element, an IO interface element, a debug support element and an internal bus interconnecting all above elements. For easy debugging, it also includes attached to the internal bus a registered boundary scan standard (JTAG) interface that accesses one or more scan chains inside the microprocessor, and is arranged for controlling DMA-type exchanges via the internal bus with other elements connected to this bus.

Abstract: The invention proposes a testing method and associated arrangement for electronic circuitry that combines functional components that are interconnected by handshake channels. Various of such channels are now provided with an inbreaking junction and an outbreaking switch as a test component pair. The junction has two passive ports and one active port. The switch has one passive port and two active ports that are selected through a passive control port. In this way inbreaking into and outbreaking from the channel is rendered feasible. Now inbreaking is done on a first channel, and outbreaking on a second channel, so that thereby all components are tested that lie between the first channel's junction and the second channel's switch.

Abstract: The invention relates to a measuring apparatus used for testing the connections between at least two subassemblies (3, 4, 5), comprising a test system (1) for generating a test signal available on an output of the test system and for evaluating an analysis signal produced by a subassembly (3, 4, 5) from the test signal and received on an input of the test system. The test system (1) is also provided for applying a switch control signal to a controller (10, 11, 12) included in a subassembly (3, 4, 5). A subassembly (3, 4, 5) includes a switching circuit (7, 8, 9) controlled by the assigned controller (10, 11, 12), which switching circuit is provided for directing a test signal or an intermediate signal formed from this test signal to a test input of a subassembly and for receiving at least a further intermediate signal from a test output of a subassembly.

Abstract: In a communication system comprising different apparatuses which are coupled together by a bus, a control instruction, for example, a remote control command may be passed on by a plurality of apparatuses to the apparatus performing the instruction. In order that the apparatus performs such an instruction only once, the control circuit in the apparatus memorizes from which source the performed instruction has been received. The identical control instructions received from the other apparatuses are ignored for a predetermined period of time.

Abstract: A device and method for removing co-channel conventional television signal interference from a digital signal by using an adaptive filter which tunes to the periodic components of the conventional television signal. The output of the adaptive filter is then subtracted from the received signal to produce an error signal. This error signal is then used to recursively update the taps of the adaptive filter. The invention also relates to the use of the adaptive filter in conjunction with a DFE.

Abstract: Device for transmitting or storing digital television pictures in which a maximum possible number of data of a group of transformed pixel blocks (DB.sub.1 . . . DB.sub.12) is transmitted in the form of variable-length code words (V.sub.1 . . . V.sub.N) in a corresponding channel block of predetermined length (FIG. 5A). If all code words of the groups of blocks are accommodated in the corresponding channel block (FIG. 5C), the channel block will also comprise surplus data of other blocks. The boundary, within a channel block, between these code words and surplus data is transmitted in the form of an address (P) which is accommodated at a predetermined position of the channel block. If the channel block length is inadequate for transmitting all code words of the group of blocks, the channel block (FIG. 5B), will comprise at least the code words which are representative of the DC coefficient and a number of important AC coefficients of each block.

Abstract: A building management system improves the regulation and controls the functioning of appliances (41, 42, 51), such as luminaires, window blinds and heating equipment in a building. The appliances are connected via a communication bus (20) to a control system (10), which performs the automatic regulation and control. To avoid rewiring the bus (20) every time that changes are made to the arrangement of the appliances and/or the lay-out of the building, transponders (40, 50) are mounted at regular fixed places in the building, which transponders transmit bus signals wirelessly to the appliances (41, 42, 51). Additionally the transponders may be provided with a receiver (50a) for two-way communication between appliances and system and for communication between the user and the system using a remote control unit (59).

Abstract: An analog-to-digital converter for converting a multitude of analog input signals into a corresponding multitude of digital signals comprises a series arrangement of an analog multiplexer (2), an oversampling sigma-delta modulator (8), a decimator-cum-low-pass filter (10), a digital demultiplexer (12), an interpolator (14) and a digital matrix (16), which are all operated in synchronism.

Abstract: Compression algorithms for digital video signals are based on processing of data blocks of frames which are of three types, i.e. intraframes, predicted frames, and interpolated or bidirectional frames (B). The memory space of the decoder is arranged in the form of five pages, four pages of which are used for each storing a field of the intraframe or predicted type. The fifth page is divided into sections each of which can store a line of blocks of a field of a bidirectional frame B. The bidirectional frames are decoded in successive stages of one line of blocks at a time, and the lines of blocks which are being decoded are stored progressively each time at the address in memory of a line of blocks the contents of which have already been displayed. The necessary memory space of the decoder is thereby reduced from six pages to five pages.

Abstract: Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.

Abstract: A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output.

Abstract: Signals from a number of NAVSTAR global positioning system (GPS) satellites (11,12,13,14) are received by a receiver (16) in a vehicle (15) and a segment of the signals is stored in a memory (18) prior to retransmission by a transmitter (19). A base station (35) receives these transmissions from the mobile unit using a first receiver (36). The base station also receives signals directly from the NAVSTAR GPS satellites using a second receiver (38). A control and calculating apparatus (37) within the base station can determine the ephemeris (course) information for the satellites and can measure the transmission times or propagation delays of signals between the satellites and the vehicle and with this information the control and calculating apparatus can calculate the position of the vehicle unit.