Abstract: Advantage is taken of the presence of ordinary parity check bits occurring in the data flow in a computer or other information-handling system to improve error correction capability while at the same time providing simpler decoding. More particularly, the encoding and decoding system, methods, and devices herein include the capability of separating error correction in data bits and in parity check bits. In this regard, it is noted that the present invention therefore provides an improved memory system in which the parity check bits do not have to be stripped off prior to storage of data into a memory system with error correction coding redundancy built in. Instead of these parity check bits being stripped off, they are incorporated into a generalized and generalizable error correction system which produces a significantly simple decoding and error correction structure.

Abstract: Storage devices are presented which have some facility of error indication and error correction. The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted. The approach of doubling only the storing elements can be extended to implement a triple storing element (10, 12, 30) in the same cell. Then, with the help of a small and simple error correction logic (32) in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell.

Abstract: Data is written to an unsegmented buffer located within shared memory. While data is being written to the unsegmented buffer, at least a portion of the data is being read from the buffer. A counter is used to indicate how much space is available in the buffer to receive data. Further, the counter is employed to ensure that the reader does not advance beyond the writer.

Abstract: Managing processor resources in a non-dedicated computer system. An amount of a processor resource is allocated to a real-time application of the computer system. The amount does not exceed a limit chosen for a group of real-time applications, wherein the group includes the real-time application being allocated the resource. A selected amount of the processor resource remains available to execute other types of applications and work on the system. During processing of the real-time application, use of the processor resource does not exceed a chosen maximum value, thereby ensuring the processor resource is not monopolized by the real-time application and allowing other types of work to be processed on the system.

Abstract: A logical partition includes at least one dedicated logical processor and at least one shared logical processor. The dedicated processor is a different type of processor than the shared processor, and/or the dedicated processor executes a different dispatching procedure than the shared processor. The use of the shared processor automatically ramps up, as the arrival rate of requests forwarded to the logical partition increases. Furthermore, the use of, the shared processor automatically ramps down, as the arrival rate decreases.

Abstract: To enable a power to the computer to be shut down in a simple configuration and independently of the status of the computer. The power switch 46 is set at the normal position while the computer 10 is operating. Each of the power, reset, and function signals is thus on the high level (A). When the function key 42A is pressed in that status, the function signal can be shifted to a low level signal so as to validate only the key 42A (B). While the power switch 46 is shifted to a pointed position and the key 42A is not pressed, only the power signal is validated, thus a power-on or power-off command can be issued (C). If the power switch 46 is set at a pointed position and the key 42A is pressed, then the level of the reset signal becomes low, thereby the reset signal is validated with the key 42A (D). Consequently, the power to the computer can be shut down forcibly if the power switch 46 is set at a pointed position and the key 42A is pressed, regardless of the status of the computer 10 operation.

Abstract: An electromagnetic shield system for cartridge-based printed circuit cards inserted into a printed circuit mother board comprises a card level system and a board level system which are electrically connected upon card insertion to provide more effective EMI shielding system. Prongs on a card level tab provide continuous EMI shielding even as card insertion operations are taking place. The principal linkage between the card level and board level systems is provided by a flexible shield strip which mates with apertures in a conductive board stiffener and simultaneously contacts not only a conductive cartridge bezel, but also contacts an EMI shield plate disposed on the printed circuit card.

Abstract: This invention allows a related set of coordinator services to migrate from one node to another without disrupting applications on any of the nodes in the system. Unlike other methods, this invention allows a set of interdependent services to be brought to “quiescence” and migrated together. Since service operations depend upon the results and/or data of other service operations, any particular operation can only complete properly when those other operations return data necessary for the completion of the dependent operation. Therefore, this invention permits the completion of non-disruptive migration by phasing the “quiescence” of the services. Operations that are most dependent upon other operations are suspended before those other operations; then the process waits for any current operations to complete.

Abstract: Apparatus for synchronizing time-of-day events across a plurality of neighboring processing nodes organized in a distributed parallel processing system with each processing node including a time-of-day (TOD) incrementor. The TOD incrementor of each processing node is coupled to a local oscillator in the processing node running at a preselected frequency to increment locally the TOD incrementor. A controller determines one of the processing nodes as the master processing node by transmitting an initialization packet to the selected processing node, and transmits a set TOD service packet to the selected master processing node. The master processing node includes a broadcast generator that broadcasts TOD update packets to neighboring processing nodes. A register in the master processing node counts a multiple of the preselected frequency.

Abstract: A printed circuit board employs a rigid toothed drive arm driven by an exterior spur gear to actuate a pair of levers pivotably attached to one end of the drive arm. Spur gear rotation moves the drive arm and variously moves the drive arm and levers into “Y” or “T” configurations, and in doing so, pushes against exteriorly mounted cabinet or enclosure pins to effect inward and outward motion of the entire board, even when it is fully populated with printed circuit cards contained in cooperatively acting cartridges.

Abstract: An electronic printed board assembly comprises a printed circuit board which employs printed circuit card connectors electrically connected to components mounted on the board. The printed circuit board includes board level guides with slots for receiving correspondingly shaped ridges disposed on outer, lower portions of printed circuit card-bearing cartridges. The guides are preferably provided on only one side for each cartridge to improve packaging density. The surface guides, together with the cartridge design, eliminate the need for physical contact with surrounding enclosures or cabinets.

Abstract: This invention provides a defragmentation utility that works on-line in parallel with other file system activities. Thus, it avoids making the file system unavailable for periods of time which would, if not for this invention, slow down data communication exchange and the execution of other tasks dependent upon the data. In particular, this invention, steps through all of the valid inodes finding each of the fragments. The defragmentation engine decides which fragments must remain in their current location and which fragments should migrate to another disk block sub-block location. Since the data blocks span across multiple disks, for each valid disk of the file system a set of disk blocks are constructed that are chosen to be filled, herein called plates. When the plates become full or reach a certain fullness, they are removed from the set and replaced by other disk blocks. When a disk block is removed from the plate set, it is moved to a “done” list as it is considered “full”.

Abstract: A backing out capability backs out a component of a computing environment, while maintaining the availability of the computing environment. In particular, a component of the computing environment which is associated with at least a portion of a unit of work is backed out from one version to another version. In addition, the backed out component is capable of emulating the other version.

Abstract: An input/output device controller supplies power to a PC card in a secure manner. A PC card is a device that is loaded into a slot of a personal computer. The input/output device controller, which permits an information processing apparatus to communicate with an input/output device, operates in a manner so that when an abnormality is detected in the supply of operating power to the PC card, the detection result is reported to the personal computer. When an abnormality in the supply of operating power to the PC card is detected, the output of a driver for the PC card is halted so as to prevent the destruction of the internal circuitry of the PC card due to latch-up problems.

Abstract: An apparatus, method and program product for resubmitting queries encompassed by a Query Management Subsystem (QMS) responsive to high availability recovery actions within itself and a database subsystem it is designed to serve. The invention includes a work queue, a database subsystem, and a first QMS server which invokes and tracks queries in the work queue (received through traditional client interface means) as delivered to the database subsystem. A Query Resubmittal Mechanism (QRM) in the QMS is responsive to the database, client, and high availability recovery actions for both the QMS and database subsystem. The QRM modifies the status of queries in the work queue depending on whether a query has been submitted to the database or a database query response has been received. Incoming client queries are placed in the work queue (with queued status Q). Completed queries from the database are removed from the work queue and answer sets returned to the originating client.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are transmitted from source nodes to destination nodes. An “eager” rendezvous transmission mode is disclosed in which early arrival buffering is provided at message destination nodes for a predetermined amount of data for each of a predetermined number of incoming messages. Relying on the presence of the early arrival buffering at a message destination node, a message source node can send a corresponding amount of message data to the destination node along with control information in an initial transmission. Any remaining message data is sent only upon receipt by the source node of an acknowledgement from the destination node indicating that the destination node is prepared to receive any remaining data.

Abstract: A method for constructing a single ECC that incorporates two codes into one is presented. This single ECC configuration can be applied to a memory configured in 2-bit-per-chip or 4-bit-per-chip. A mode bit M is used to indicate one of the two memory configurations.

Abstract: A cartridge is provided for the insertion and removal of printed circuit cards from a printed circuit board. The cartridges are self-contained and employ board level guides for establishing a position from which the force of card insertion can be withstood. The cartridges include an external actuating lever which also preferably operates a portion of an EMI shield system which is integrated with the circuit board. The cartridge tops also interlock to provide additional overall structural rigidity.

Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.