Patents Represented by Attorney, Agent or Law Firm Lawrence D. Cutter
  • Patent number: 6507863
    Abstract: A Dynamic Multicast Routing (DMR) facility is provided for a distributed computing environment having a plurality of networks of computing nodes. The DMR facility automatically creates virtual interfaces between selected computing nodes of the networks to ensure multicast message reachability to all functional computing nodes within the distributed computing environment. The DMR facility employs a group of group leader nodes (GL_group) among which virtual interfaces for multicast messaging are established. Upon failure of one of the group leader nodes, another computing node of the respective network having the failing group leader node is assigned group leader status for re-establishing virtual interfaces. Virtual interfaces are established between the group leader nodes such that redundancy in message routing is avoided.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventor: Marcos N. Novaes
  • Patent number: 6496840
    Abstract: Write requests are performed against one or more resources of a resource group in a persistent and atomic manner. When a write request is received, a backup resource group is updated to reflect data in a current resource group. Thereafter, the write request is performed against the backup resource group. After successfully performing the write operation(s), the backup resource group and the current resource group are swapped in an atomic, consistent manner, such that the backup resource group is now the new current resource group.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Rosario A. Uceda-Sosa, Steven R. Champagne, Kailash N. Marthi, Gregory D. Laib
  • Patent number: 6493235
    Abstract: A guide structure and matching printed circuit card carrying cartridge provides hot pluggability functionality even when electronic circuit components need to be disposed in very tight spaces. The guide structure includes front and rear portions linked by slot-defining rungs. Front and rear apertures provide alignment and/or locking functions. The guide structure is easily manufacturable from a single sheet of metal which is stamped and formed to meet all desirable design specifications. A matching self-contained docking cartridge is provided with mating parts for these apertures. EMI shielding and cooling functions are also accommodated.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis R. Barringer, Budy D. Notohardjono, Edward J. Seminaro, Harold M. Toffler
  • Patent number: 6490693
    Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. Briskey, Marcos N. Novaes
  • Patent number: 6487678
    Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which resulted from a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. Briskey, Marcos N. Novaes
  • Patent number: 6480897
    Abstract: A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christine M. Desnoyers, Douglas J. Joseph, Francis A. Kampf, Alan F. Benner
  • Patent number: 6464530
    Abstract: A strain relief for a plurality of cables comprises two portions which act together to clamp the cables in position without the use of tools in a manner which is intuitive to a user. The first portion has hook elements projecting from a surface, each hook element being for retention of a cable. A second set of hook elements is also provided. A second portion has a cable receiving opening corresponding to the cable receiving opening in the first portion. The second portion latches to the first portion, so as to clamp the cables.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: October 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter Andrew Smith, Ian McFarlane Denny, Joseph James Hall
  • Patent number: 6463563
    Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6462694
    Abstract: A priority encoding technique is provided which outputs a code corresponding to the highest-priority input line among input lines having a true value when true values are input to more than one of the input lines, which are prioritized and given codes. The technique includes performing higher-order-bit encoding by outputting higher-order bits corresponding to the group having its highest priority among those groups distinguished by the higher-order bits to which true values are input; and performing lower-order-bit encoding to output lower-order bits corresponding to the input line having the highest priority among input lines to which the true values are input. Further, the lower-order-bit encoding includes invalidating the input of true values into the input lines to groups having lower priorities than the highest-priority group distinguished by the higher-order bits.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventor: Hisatada Miyatake
  • Patent number: 6460068
    Abstract: A fractal process scheduler for testing applications in a distributed processing system having a plurality of nodes. The scheduler includes an originating file containing a sequence of statements, each statement representing a fractal cell, an input file comprising statements from said originating file which generate vertices, a fractal parser for compiling the statements from the input file, one or more intermediate files produced by the fractal parser comprising intermediate results. The intermediate files are executable for scheduling a process of the application being tested to nodes of the distributed processing system. The schedular further includes a master file produced by said fractal parser, said master file which is executable for scheduling a process of the application being tested to nodes of the distributed processing system. The fractal parser maps the input file into the intermediate file and the master file in accordance with complex fractal expansions.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventor: Marcos N. Novaes
  • Patent number: 6460157
    Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6459408
    Abstract: An object of the present invention is to inform a person who adjusts the direction of an antenna 70 of the intensity of a signal received by the antenna 70 without connecting or adding special equipment to the antenna 70 or a connection cable 74. The satellite receiver 20 comprises: a received intensity information outputting means 22 for outputting received intensity information describing the intensity of a signal received from the antenna 70; a modulating means 30 for superimposing the received intensity information on a carrier wave; and a superimposing means 40 for superimposing the carrier wave carrying the received intensity information on a connection cable 74.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Hiroaki Kubo, Masahiro Murakami
  • Patent number: 6460175
    Abstract: A program product recorded on a computer readable medium in which the program product includes a method of performing a software operation on a target of one or more processors in a distributed processing system wherein another processor is designated as a server.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard Ferri, Richard C. Russell
  • Patent number: 6457154
    Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6442583
    Abstract: A method for managing a workload distributed across data processing systems in accordance with a common processor consumption standard, including the steps of measuring the processor consumption of the work units to create local processor consumption data; sending the local processor consumption data to at least one other system; receiving processor consumption data from at least one other system to create remote processor consumption data; and adjusting at least one of the system control parameters to modify the remote processor consumption and the local processor consumption of the work units to achieve the common processor consumption standard is provided. Also provided is an apparatus according to the method.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Catherine Krueger Eilert, Bernard Roy Pierce
  • Patent number: 6418519
    Abstract: A write-behind computer program product is presented which allows writing data to multiple volumes of storage media associated with one or more server nodes in a distributed processing environment. A client application on a client node writes blocks of data to a first magnetic tape of a first server node until an end of physical storage of the first magnetic tape is reached, without having predetermined the size of the first magnetic storage. Thereafter, the writing of blocks of data is switched to a second magnetic tape, which may be on the first server node or a second server node in the system. The writing and switching process can repeat a number of times across multiple magnetic tapes. Data is written in a write-behind operation and the switching to a new magnetic tape occurs transparent to the client application, and without loss of data.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: July 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: William S. Cadden, Rong S. Lee, Oystein Skudal
  • Patent number: 6415332
    Abstract: Message-passing capability is provided in a computer system with a plurality of asynchronous computing nodes interconnected for transmission of messages between threaded user tasks executing in ones of the computing nodes. A message is received at a receiver computing node employing a threaded message passing interface (MPI), which includes a means by which a user-defined program can be called by an interrupt service thread at the MPI. The user-defined program takes a predefined action in response to the asynchronous arrival of the at least one message packet. For example, the user-defined program might comprise a program to initiate a function to receive the at least one message packet at the receiver's threaded MPI, which may include awaking a waiting thread.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventor: William G. Tuel, Jr.
  • Patent number: 6412018
    Abstract: Message-passing capability is provided in a computer system with a plurality of asynchronous computing nodes interconnected for transmission of messages between threaded user tasks executing in ones of the computing nodes. A message is received at a receiver computing node employing a threaded message passing interface (MPI), which includes a means by which a user-defined program can be called by an interrupt service thread at the MPI. The user-defined program takes a predefined action in response to the asynchronous arrival of the at least one message packet. For example, the user-defined program might comprise a program to initiate a function to receive the at least one message packet at the receiver's threaded MPI, which may include awaking a waiting thread.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: June 25, 2002
    Assignee: International Business Machines Corporation
    Inventor: William G. Tuel, Jr.
  • Patent number: 6406322
    Abstract: A preferred embodiment of an easily loadable self-contained cartridge for printed circuit card insertion and removal comprises a top wall and a front conductive bezel which is pivoted at its top with the top of the box wall. A set of three linked arms with an actuating arm extending through and affixed to the bezel provides a mechanism for moving a card-bearing movable carrier. One end of the set of linked arms is affixed to the top wall and a middle arm includes a pin which rides in a slot in the carrier to effect the desired vertical carrier motion which moves a printed circuit card edge connector into and out of a board level connector. The carrier includes slotted clips for holding the printed circuit card at one or more corners. The carrier is adjustable. A side wall includes a ridge which mates with board level guides.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: June 18, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis R. Barringer, Edward J. Seminaro, Harold M. Toffler
  • Patent number: 6401216
    Abstract: A checkpoint of a parallel program is taken in order to provide a consistent state of the program in the event the program is to be restarted. Each process of the parallel program is responsible for taking its own checkpoint, however, the timing of when the checkpoint is to be taken by each process is the responsibility of a coordinating process. During the checkpointing, various data is written to a checkpoint file. This data includes, for instance, in-transit message data, a data section, file offsets, signal state, executable information, stack contents and register contents. The checkpoint file can be stored either in local or global storage. When it is stored in global storage, migration of the program is facilitated. When a parallel program is to be restarted, each process of the program initiates its own restart. The restart logic restores the process to the state at which the checkpoint was taken.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kalman Zvi Meth, Anton Prenneis, Adnan M. Agbaria, Patrick Francis Caffrey, William Joseph Ferrante, Su-Hsuan Huang, Demetrios K. Michailaros, William Gole Tuel, Jr.