Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery module with secure identity information includes: (1) a tamper resistant processing environment 200 located within the battery module 110 and (2) a key generator configured to generate a key based on an identity of the battery module 110 and cause the key to be stored within the tamper resistant processing environment 200.

Abstract: A printed circuit cable assembly (PCCA) for a hard disk drive (HDD) is disclosed. The PCCA includes a stiffener portion having an elongated shape that includes an integrated circuit (IC) chip. The PCCA also includes a flexible portion extending from the elongated stiffener portion, wherein the PCCA is configured to be mountable on a headstack of the HDD such that an entire footprint of the IC chip overlays a metallic portion of the headstack of the HDD.

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: The objective of this invention is to provide a motor control device, and a disk drive device using the same, in which during emergency operation it is possible to supply necessary power to the motor while limiting enlargement of the circuit area. During the retraction operation, control is performed to alternate between a short-circuit mode in which each terminal U, V, W of the spindle motor M1 is short-circuited to the terminal ICOM, and a rectifying mode in which the back electromotive force of the spindle motor M1 is rectifies and output to the power supply line ISO3V, VGND while the input of power from the power supply line ISO3V, VGND to the spindle motor M1 is blocked.

Abstract: Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power.

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate initially being zero kilobits per second. This results in a quality of service QoS, optionally measured at the sender or the receiver. When the QoS is on an unacceptable side of a threshold of acceptability, the sender sends diversity packets at an increased rate. Increasing the diversity rate while either reducing or maintaining the overall transmission rate is new. CELP-based multiple-description data partitioning sends the base or important information plus a subset of fixed excitation in one packet and sends the base or important information plus the complementary subset of fixed excitation in another packet. Reconstruction produces acceptable quality when only one of the two packets is received and better quality when both packets are received. Reconstruction provides for single and multiple lost packets.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A disk drive data storage system comprising at least one data storage disk and a sensor assembly proximate the data storage disk. The sensor assembly further comprises circuitry for writing data to the data storage disk and circuitry for reading data from the data storage disk. The system also comprises circuitry for controlling the circuitry for reading data during different time periods so that the circuitry for reading data consumes different levels of power while the circuitry for writing data is writing data to the data storage disk.

Abstract: A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further comprises an interface adapter counting a number of inert scans in the command window, and the number of inert scans defines a particular command or data. An inert scan results in no data being moved into or out of the interface adapter.

Abstract: Low noise amplifier circuit. The low noise amplifier circuit includes an amplifier that amplifies an input to provide an output. The amplifier is coupled to an input terminal. The circuit also includes a device in a cascode connection with the amplifier. The circuit further includes a tuning circuit coupled to the device to phase shift the output. Further, the circuit includes a feedback circuit that is responsive to a phase-shifted output to enhance gain of the amplifier. The feedback circuit is coupled to the tuning circuit and the amplifier.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: A microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller further includes a selection register and a data structure. The data structure comprises a plurality of associated field sets. Each bit position in the selection register indexes to one of the associated field sets in the data structure, and the value contained in each such bit position indicates whether or not to select the corresponding associated field set for selection of an analog input channel. Each associated field set comprises one or more values collectively specifying an analog input channel to select for conversion to digital form.

Abstract: A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.

Abstract: A switched power amplifier contained in a circuit is implemented to receive a single-ended input signal and generate a single-ended output signal, the single-ended output signal being a power-amplified version of the single-ended input signal. The switched power amplifier provides high efficiency.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.