Patents Represented by Attorney, Agent or Law Firm Lawrence J. Bassuk
  • Input linking circuitry connected to test mode select and enables
    Patent number: 8112684
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Serial compressed data I/O in a parallel test compression architecture
    Patent number: 8112685
    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Tap control of TCA scan clock and scan enable
    Patent number: 8108742
    Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 31, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Multiplexer selecting STP clock signal with tap control outputs
    Patent number: 8099641
    Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 17, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Formatter selectively outputting scan stimulus data from scan response data
    Patent number: 8099642
    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 17, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Serial scan chain in a star configuration
    Patent number: 8095840
    Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Clock and mode signals controlling data communication in three states
    Patent number: 8094765
    Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Position independent testing of circuits
    Patent number: 8095839
    Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Transitioning through idle 1, 2 and sequence 1 machine states
    Patent number: 8095838
    Abstract: A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Synchronizing TAP controllers with sequence on TMS lead
    Patent number: 8078898
    Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: December 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • Removing local RAM size limitations when executing software code
    Patent number: 8078842
    Abstract: An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: December 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Gerard Chauvel, Jean-Philippe Lesot
  • Wrapper leads gating TAP instruction and data registers
    Patent number: 8078927
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: December 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Inverted TCK access port selector selecting one of plural TAPs
    Patent number: 8065578
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Dual controllers for scan paths, distributors, and collectors
    Patent number: 8065577
    Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Producing STTD diversity signal from rake combined level 3 message
    Patent number: 8059746
    Abstract: A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output signal corresponding to a magnitude of the input signal. A control circuit (726) is coupled to receive the output signal, a first reference signal (.eta..sub.1) and a second reference signal (.eta..sub.2). The control circuit is arranged to produce a control signal in response to a comparison of the output signal, the first reference signal and the second reference signal.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: November 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Ganesh Dabak, Timothy M. Schmidl, Srinath Hosur
  • RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA transceiver employing the same
    Patent number: 8060027
    Abstract: The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: November 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Muhammad, Dirk Leipold
  • TAP interface outputs connected to TAP interface inputs
    Patent number: 8055967
    Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Comparing supplied and sampled link ID bits on TMS lead
    Patent number: 8055947
    Abstract: An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Primary, secondary, and tertiary codes synchronizing slots in a frame
    Patent number: 8054861
    Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Sundararajan Sriram
  • Testing IC functional and test circuitry having separate input/output pads
    Patent number: 8055962
    Abstract: Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Richard L. Antley, Lee D. Whetsel