Abstract: A surveillance system for monitoring the dispensing of prescribed medication to insure that the proper patient is, in fact, being administered the prescribed medication and dosage, and that the patient for whom the medication is prescribed is so identified, before the medication is administered. To assure that the proper patient is receiving the prescribed medication, both a photograph and a description of the medication and dosage is imprinted on a label affixed to any means used to transport the medication to the patient. The label may also contain other vital patient information such as patient allergies and anticipated adverse reactions to the medication and other instructions for the well being of the patient.
Abstract: A method of maintaining a close surveillance over and the monitoring of the dispensing of prescribed medication, to insure that the proper patient is, in fact, being administered the prescribed medication and dosage, and that the patient for whom the medication is prescribed is properly identified or recognized, before medication is administered. To assure that the proper patient is receiving the prescribed medication, both a photograph and a desription of the medication and dosage is imprinted on a label affixed to a means for transporting the medication to the patient. The label may also contain other vital patient information such as patient allergies and any anticipated adverse reactions to the medication and other instructions for the well being of the patient.
Abstract: A method, and its associated system, for maintaining a close and accurate security surveillance of both the passengers and their baggage on a public conveyance, to insure that, before departure, baggage is not loaded aboard the conveyance without a prior, positive indication that the owner or the passenger has, in fact, been properly boarded.
Abstract: In order to reduce the mechanical stress that occurs at the interface of a layer of a refractory metal silicide and a layer of silicon dioxide, it is proposed that a buffer layer of polycrystalline silicon be interposed between the two layers. To accomplish this and prior to forming contact openings, the buffer layer of polycrystalline silicon is deposited on the layer of silicon dioxide and the structure is then provided with an apertured mask to define the contact openings. The structure is then initially etched through both the buffer layer and the underlying layer of silicon dioxide in order to expose portions of the buried contact regions followed by a second etch of only the buffer layer to only expose portions of the layer of silicon dioxide in order to form a gate member and any required interconnects. The process further includes the formation of a layer of metal silicide on the interconnects, in the contact openings and on the gate member.
Abstract: An electrically alterable, nonvolatile floating gate memory device is described wherein the floating gate is a second level polysilicon layer. The first level polysilicon layer is provided with an aperture in order for only a small portion of the second level polysilicon floating gate to extend through the aperture for coupling to the substrate. Chip area is conserved by coupling the floating gate to the substrate at the portion of the channel region that conduction takes place by means of the self aligned aperture.
Abstract: A process for forming reliable contacts in a VLSI device wherein, after the source and drain regions have been formed, the contact openings are formed and the source and drain regions redoped. A heat treatment step anneals surface damage and causes lateral migration of the implanted ions to preclude the contact from forming a short circuit between the doped region and the substrate exposed as a result of any misalignment of the contact openings. As an added benefit, the process also prevents the contact from "spiking" through the doped region to the underlying substrate.
Abstract: A novel process is described for the removal of the objectionable point (tilt projection, appearing at the top of a silicon island). The process includes the formation of a thick insulating layer on the top surface of the island, etching the top and sides of the insulating layer to expose, at the least, the objectionable point and, thereafter, etching the objectionable point to produce a rounded edge.
Abstract: A pair of protection circuits, each forming a silicon controlled rectifier (SCR) for protecting a circuit against either negative or positive voltage transients, are formed in a single isolated region together with a bond pad. A second embodiment also includes a sense resistor in the isolated region.
Abstract: An integrated circuit overload protection device is used to protect a bipolar transistor used in the common emitter configuration. The protective device comprises a bipolar transistor of opposite type to the protected amplifying transistor. The protective transistor is connected with its base to the collector of the amplifying transistor and with its collector connected to the terminal of the power supply which is not connected to a terminal of the load resistor of the protected device. The emitter of the protective device is preferably connected to the base of the protected device through a protective resistor. Inputs to the protected transistor are provided at the interconnection of the emitter of the protected device with one terminal of the protective resistor.
Abstract: A novel process for fabricating low resistance contacts for high density integrated circuits is described wherein during the initial processing of the device, after a scaled MOSFET is formed, contact openings, having vertical walls with respect to the underlying substrate, are provided. An apertured masking layer, having apertures which provide an open are a somewhat larger than the original contact opening, is formed on the structure after which, the structure is subjected to a high energy deep implant step followed by a low energy, shallow, supplemental implant step. The high energy implant serves to provide the device with a deep junction at the contact area to minimize spiking and, by reason of the shallow implant, good ohmic contact may be made. Since the oxide surrounding the contact opening is also implanted, there is provided means for tapering the edges of the contact opening.
Abstract: An electrically alterable, nonvolatile floating gate memory device is described having enhanced write efficiency by reason of an extension of the floating gate member. The extension is made to extend over the drain line of an adjacent memory device and serves to provide the floating gate member with additional capacitance during the write operation thereby permitting a higher write efficiency for a given voltage.
Abstract: A movable control or reception chamber is provided at the loading-unloading chamber of a diffusion furnace to control the environment around the wafers both before and after the wafers are removed from processing in the furnace tube. The reception chamber is capable of controlling the heat-up temperature prior to insertion of the wafers into the furnace while during the cool-down phase the heat given off is both controlled and prevented from being dissipated into the room.
Abstract: An improved self-aligned conductive gate member formed by suppressing or decreasing the size of the as-deposited grains of polysilicon and by suppressing further grain growth which may occur during a subsequent annealing or processing step. By maintaining the as-deposited grains as small as possible, the initiation of intergranular voids is minimized. This is accomplished by forming a low resistivity oxygen doped polycrystalline silicon layer in place of the conventional polysilicon.
Abstract: A method of reducing the time and temperature for either flowing or re-flowing a glass layer on a semiconductor device is described. The method involves conducting the flow or re-flow process steps at an elevated pressure which reduces both the time and the temperature required to achieve proper flow and re-flow characteristics.
May 17, 1982
Date of Patent:
December 13, 1983
Chung W. Leung, Robert H. Dawson, Martin A. Blumenfeld, Dennis P. Biondi
Abstract: A novel, nonvolatile floating gate memory structure is described wherein the floating gate is substantially shielded from the substrate by the control gate. The control gate is provided with a pair of apertures, through which portions of the floating gate extends. One aperture serves as means for "writing" and "erasing" while the other aperture serves as means for "reading".
Abstract: A method for forming closely spaced conductors suitable for use, for example, in CCD's and MESFET's is described utilizing an edge diffusion technique to convert exposed edge portions of a polycrystalline silicon layer to a non-etchable form. The converted portions are precisely and accurately formed to serve as spacers, thereby defining a narrow gap between adjacent conductive lines.
Abstract: A method of forming metal lines is described for semiconductor processing wherein a line mask is initially ion milled to provide a mask contour which promotes the onset of chemical etching at the base of the mask. This produces a metal line that has a tapered cross-sectional dimension wherein the base of the line is narrower than the top.
Abstract: Disclosed is a protection circuit which may be used, for example, in a television receiver to protect circuitry formed within an integrated circuit from damage due to excessively high voltage transients. The protection circuit comprises a PNPN structure forming a silicon controlled rectifier (SCR) and metal-oxide-semiconductor (MOS) transistor integral to the SCR structure. The SCR and the MOS transistors are arranged to form a two terminal protection circuit which is rendered conductive when the potential difference across the two terminals is greater than a predetermined threshold. One terminal of the protection circuit is connected to an input or output signal terminal of the protected circuit, and the other terminal is connected to a reference terminal to which a reference potential such as ground potential is applied.
Abstract: A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.