Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A transport system for the implementation of electrolytic deposition, coating or etching; and more particularly, an apparatus for selective electrolytic metallization and deposition utilizing a fluid head arrangement. A method is provided for making and maintaining an electrical contact with a product being processed in a transport system employed for selective electrolytic metallization and deposition, coating or etching. The method of making and maintaining an electrical contact with a product being processed may be utilizing a fluid head arrangement.

Abstract: A method for protecting tin oxide coated solder surfaces against further oxidation and a method for fluxless solder joining of such surfaces is provided.

Abstract: For a mulitlayer chip carrier module a computer program receives a large plurality of module design parameters and provides as output a graphical representation of the design together with text files that rate module wireability, including die pad position, attachment of each die pad to its BGA pad, and net cross-over; and quantifies the number of redistribution layers; summarizes input parameters; creates a truth table for rating wireability and thermal requirements; and provides cost sensitive parameters.

Abstract: A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.

Abstract: Plastic ball grid array (PBGA) packages comprised of organic carriers on which are mounted and encapsulated semiconductor chips, providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A heat sink for a transceiver optoelectronic module including dual direct heat paths and structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.

Abstract: The present invention provides a through-hole structure for connecting a connector to a printed circuit board, the through-hole structure comprising a signal through-hole having a conductive layer therein for supplying a signal to the printed circuit board, power through-holes having a conductive layer therein for supplying power to the printed circuit board, and dielectric constant adjusting portions formed among the signal through-hole and the power through-holes. Moreover, the present invention provides a printed circuit board having the above-described through-hole structure formed therein.

Abstract: A method and system for identifying parameters that are important in predicting a target variable. The method comprises the steps of compiling training data, said training data identifying, for each of a first set of subjects, values for each of a first set of parameters; and compiling test data, said test data identifying, for each of a second set of subjects, values for each of a second set of parameters, said first and second sets of parameters having at least a plurality of common parameters. The method comprises the further steps of using the data in the training data, and using a nearest neighbor procedure, to identify, for each of the second set of subjects, a value for a target parameter; and processing the training data and the test data, according to a predefined procedure, to determine the relative importance of at least selected ones of the first group of parameters in predicting the values for the target parameter.

Abstract: A transfer fluxing apparatus is provided. The apparatus is a flux reservoir for holding flux, a compliant pad attached to an opening in the flux reservoir and a means for controlling deposition of flux onto the compliant pad. The apparatus can be attached to an automated component placement machine. In the preferred embodiment of the invention, the control means is a valve located within the flux reservoir. The valve is opened by applying pressure to a plunger that extends through the compliant pad. When the plunger is pressed, the valve opens, and flux falls onto the compliant pad. Flux then passes through the pad to a component placement site. A method for automated fluxing and to component placement also is provided.

Abstract: A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Abstract: A printed circuit board or card having plated through-holes is provided wherein plated through-holes are filled with a photocured polymerized composition. Also, a method for fabricating these printed circuit boards or cards is provided. Also provided are compositions and methods of providing carrier films coated with the compositions for use in filling vias or plated through-holes.

Abstract: A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

Abstract: An organic solvent is separated from a waste stream comprising hydrofluoric acid, an organic solvent and etchant contaminants. The process comprises separating the hydrofluoric acid by subjecting the waste stream to at least one of the following processes: ion exchange; extraction of the hydrofluoric acid; electrophoresis; converting the hydrofluoric acid to an insoluble salt; to thereby obtain a first composition containing the hydrofluoric acid and a second stream containing the organic solvent and being substantially free of the hydrofluoric acid; and then distilling the second stream to recover the organic solvent free of the etching contaminants.

Abstract: A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.