Abstract: A method for reducing the number of wire-bond loop heights which are required in comparison with a total quantity of power and signal rings employed in low profile wire-bond integrated circuit packages. There are also provided low profile wire-bond packages which are produced in accordance with the method pursuant to the invention.

Abstract: A chip package includes a die having an active surface and an inactive surface. An adhesive is formed on the inactive surface where the adhesive has a low Young's modulus of elasticity. The low Young's modulus of elasticity may be 10,000 psi or less; 1,000 psi or less; or, preferably, about 1,000 psi. Further, the adhesive may include a thermal conducting material. A protective plate is coupled to the inactive surface using the adhesive and a chip carrier is coupled to the active surface of the die.

Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.

Abstract: An apparatus and method attaching a heatsink to a surface of an electronic package comprising a substrate, an integrated circuit chip attached to the surface of the substrate, an encapsulant encapsulating the integrated circuit chip and contacting at least a portion of the surface of the substrate, and an orifice formed in the top portion of the encapsulant to attach the heatsink to the surface of the electronic package. The heatsink may be attached and removed as desired to allow for package identification or rework.

Abstract: A fixture for aligning the leads of SMT components with the corresponding pads of the printed circuit board, which is to receive such components, before soldering the leads to the pads. The fixture includes clamps for applying forces directly to the leads of the SMT components, alone or in conjunction with the clamping forces which are traditionally applied to the body of the component, the applied forces sufficient to seat the leads on the corresponding pads. In a preferred embodiment, the forces are applied by providing the fixture with a series of rocker-type clamps, each having an edge for engaging the several leads associated with a particular SMT component to be joined to the printed circuit board. The clamp is preferably constructed of a non-wettable material so that the edge of the clamp will not be wet by the molten solder during the soldering procedure, and the edge is preferably thin so that the clamping surface in contact with a particular lead is minimized.

Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.

Abstract: A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive levels thereof, wherein the conductive levels are formed on a dielectric material having a low dielectric constant and low thermal conductivity. One or more cooling posts, e.g., multiple thermally conductive plugs are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive levels and thermally coupled thereto so that heat produced by conductive lines within the wiring levels is transferred into and through the cooling posts for forwarding to a supporting substrate, which may have a back surface coupled to a cold plate, or to an upper surface of the semiconductor chip structure. The thermally conductive plugs of each cooling post have a second thermal conductivity, and the first thermal conductivity is less than the second thermal conductivity, for example, one third or less.

Abstract: A process for making a removably interlockable connector assembly that includes a first connector having a head on a mesa and a second connector having an opening that receives the head on the first connector. The head on the mesa of the first connector and the material defining the opening in the second connector are flexible and sized, so that the head on the mesa of the first connector and the material defining the opening in the second connector flex as the head on the mesa of the first connector is inserted into the opening in the second connector. The head on the mesa of the first connector is formed by selectively etching portions of a first pad layer through openings in an etch resistant layer.

Abstract: A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: Electrolytic plating of a workpiece is enhanced by providing a resistor between the workpiece and electrically conductive support member.

Abstract: A circuitized semiconductor structure comprising a layer of dielectric material, a catalyst seed layer above the layer of dielectric material, a layer of photoimageable dielectric material on the catalyst seed layer and having openings therein, a nickel layer in the openings and a layer of copper in the openings above the nickel layer and being coplanar with the top of the layer of dielectric material is provided, along with a method for its fabrication.

Abstract: A process for promoting fluxless soldering of a mass of bulk solder having a bulk ratio of a first metal to a second metal, such as lead-enriched solder that has significantly more lead than tin. The process comprises exposing the bulk solder to energized ions of a sputtering gas in the presence of a halogen, such as fluorine, and forming a surface layer having a desired surface layer ratio of the first to the second metal that is less than the bulk ratio, the surface layer further comprising an uppermost surface film containing the fluorine or other halogen. After the solder exposure and surface-layer formation, the process may further comprise electrically joining the solder to a surface without using externally-applied flux. This process enables the joining step to be performed at less than 300° C., at approximately 180° C.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: A method and apparatus for testing through the connector of a circuit card. The apparatus includes a block, which may be tapered, to offset the force applied when engaging the connector. The block is adjustably mounted to accommodate testing of different-sized circuit cards.

Abstract: A Method for detecting misalignment of layers of a multi-layer circuit board. A Plurality of layers of electrically insulating material are formed. At least one artwork feature is formed on a surface of at least one of the layers of electrically insulating material in the vicinity of at least One edge of the at least one layer of electrically insulating material. At least one reference point is formed on the at least one layer of electrically insulating material. The layers of electrically insulating material are joined together. The at least one artwork feature is exposed by removing a portion of the at least one layer of electrically insulating material. A location of the at least one artwork feature relative to the at least one reference point is visually determined, thereby detecting misalignment of the layers of electrically insulating material.

Abstract: An interposer for connecting two circuit members. The interposer has two extending conductive ends, is “Z” shaped, and has a center of gravity positioned relative to one of the conductive ends such that the interposer is capable of standing upright upon that end without external support. The interposer may be composed of a plated metal, and at least one of the extending conductive ends may have deposited dendrites or a raised bump. The Z-shaped interposer prevents bowing or cracking of the connected structure which otherwise occurs during use due to the different thermal coefficients of expansion of the two circuit members.

Abstract: A method of repairing wiring shorts on a surface of an organic layer. The organic layer, which is preferably a SLC/ASM layer, may be a surface layer of a Printed Circuit (PC) board. The absorption spectrum of the organic layer is examined. Based on that absorption spectrum, a laser is selected with a wavelength such that the surface layer slightly absorbs, 1-10%, laser energy striking it. Thus, the laser removes metal on the surface, while slightly etching the surface layer and without effect on any metal buried in or beneath the surface layer. Preferably, the laser is an Nd:YAG laser having a wavelength in a range where the ASM layer absorption is between 2-5%, and the copper ablation rate is high.