Abstract: Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.

Abstract: There is disclosed a two-piece electrical connector assembly having a first electrical connector and a second electrical connector. The first electrical connector includes a plurality of first signal conductors disposed along first and second sides of a first insulative housing and first ground plates disposed along the first and second sides of the first insulative housing and positioned adjacent the plurality of first signal conductors. The first electrical connector defines a slot for receiving an edge of a first printed circuit board. The second electrical connector includes a plurality of second signal conductors disposed along first and second sides of a second insulative housing and second ground plates disposed along the first and second sides of the second insulative housing and positioned adjacent the plurality of second signal conductors.

Abstract: Automatic test equipment for testing non-deterministic packet data from a device-under-test is disclosed. The automatic test equipment includes a memory for storing expected packet data and a receiver for receiving the packet data from the device-under-test. A data validation circuit is coupled to the receiver for validating non-deterministic packet data based on the expected packet data from the vector memory.

Abstract: A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

Abstract: A clock system is disclosed for distributing and generating a digital clock signal for a plurality of electronic assemblies. The clock system includes a remote fixed-frequency clock for generating a first clock signal of a first frequency and a plurality of local clock modules. The local clock modules are respectively disposed on the plurality of electronic assemblies and each include synthesizer circuitry for creating a variable clock signal of a different frequency than the first frequency. Fanout circuitry is coupled between the remote fixed frequency clock and the plurality of local clock modules to distribute the first clock signal.

Abstract: An interface for a bus test instrument is readily adaptable for testing a wide range of bus types. The interface includes a pair of transmit lines and a pair of receive lines. A transmitting circuit is adaptable for transmitting either single-ended or differential signals over the transmit lines, and at least one receiving circuit is adaptable for receiving either single-ended or differential signals from either the receive lines or the transmit lines. The flexible interface allows the testing of single-ended and differential busses, as well as busses that support both unidirectional and bidirectional communication.

Abstract: A method and apparatus for pre-qualifying lines with respect to estimating the insertion loss of the line is presented. End-to-end insertion loss at high frequencies is estimated from measurements made at low frequencies through the voice switch at the central office of a telephone company. An AC voltage waveform is applied to the telephone line being tested. Real and imaginary components of the resultant waveform are measured. These measurements are captured and used to estimate the insertion loss of the telephone line at frequencies in the range of 40 kHz to 300 kHz.

Abstract: A method characterizes a customer line for data transmission. The method includes measuring electrical properties of the customer line from a central location, identifying a line model from the measurements, and identifying a modem model for a modem selected for use with the customer line. The modem model gives performance data for the selected modem. The method also predicts performance data for the customer line when operated with the selected modem by combining the line and modem models.

Abstract: A differential delay cell is disclosed. The delay cell includes a voltage bus and a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output. A current source is disposed at the current node while a differential diode-connected load is disposed between the differential pair and the voltage bus. The differential diode-connected load comprises at least one n-channel MOS transistor configured as a diode.

Abstract: A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

Abstract: A technique for measuring spectral components, such as noise and distortion, of a non-coherently sampled test signal containing at least one tone of known frequency includes modeling the spectral components of the at least one tone, including the effects of leakage, based upon frequency of the at least one tone and a plurality of known sampling parameters. A DFT is taken of the sampled test signal, and the DFT is adjusted based on the modeled spectral components. The adjusted DFT is substantially leakage-free and directly reveals spectral components of the test signal, including low-power components that would ordinarily be lost in the leakage errors.

Abstract: A printed circuit board assembly adapted for immersion cooling is disclosed. The assembly includes a first circuit board having a first device side with a first portion configured to mount a first plurality of semiconductor devices. A second circuit board having a second device side with a second portion configured to mount a second plurality of semiconductor devices is disposed in confronting parallel relationship to the first circuit board. The assembly further includes a border element interposed between the first and second boards and disposed around the respective first and second portions. The border element cooperates with the first and second boards to form a liquid-tight container. An inlet formed in the border receives an electrically nonconducting liquid that is subsequently discharged through an outlet.

Abstract: A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

Abstract: There is disclosed an electrical connector assembly having a first electrical connector mateable to a second electrical connector. In one embodiment, the first electrical connector includes a plurality of wafers, with each wafer having an insulative housing, a plurality of signal conductors and a shield plate. A portion of the shield plate is exposed so that a conductive member can electrically connect the shield plates of the wafers at the exposed portion of the shield plate. In one embodiment, the second electrical connector includes an insulative housing, and a plurality of signal conductors and ground conductors in a plurality of rows. Each row corresponds to a wafer of the first electrical connector. Each signal conductor has a contact tail and each ground conductors has two contact tails.

Abstract: A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.

Abstract: Automatic test equipment is disclosed including a console and a testhead cooled by a hybrid cooling system. The testhead includes a card cage assembly having a plurality of slots disposed in spaced-apart relationship and adapted for receiving a plurality of electronic board assemblies. The hybrid cooling system includes a first cooling assembly coupled to the card cage assembly for distributing a first cooling medium proximate the electronic board assemblies and a second cooling assembly. The second cooling assembly is disposed proximate the card cage assembly and includes user-activatable cooling ports for selective access to a second cooling medium for the electronic board assemblies.

Abstract: A method for forming conductor structures on a semiconductor wafer is provided. The method begins with depositing a seed layer having a substantially consistent thickness over a barrier layer that covers the features and the field regions among them. The process continues with electrodepositing a planar copper layer on the seed layer and subsequently electroetching it until a thinned seed layer remains over the field regions. When another layer of planar copper is deposited on the remaining copper in the features and on the thinned seed layer on the field regions, this structure minimizes stress related defects in the features which occur during a following anneal process.

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, using an indirect external influence, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion, thus causing greater plating of the cavity portion relative to the top portion.

Abstract: A channel architecture for use in automatic test equipment is disclosed. The channel architecture comprises pattern generation circuitry and timing circuitry responsive to the pattern generation circuitry to generate timing signals. Formatting circuitry coupled to the output of the timing circuitry generates pulse waveforms for application to pin electronics circuitry. The pin electronics circuitry is responsive to the formatting circuitry for interfacing the automatic test equipment to a device-under-test. The pattern generation circuitry, the timing circuitry, the formatting circuitry and the pin electronics circuitry are formed on the same integrated circuit.

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.