Abstract: A receiver estimates a channel parameter from a received signal. The channel parameter may a DC signal level, a carrier to interference ratio, a noise spectrum, or the like. The receiver performs channel equalization and produces estimated symbols. The estimated symbols are remodulated and the channel parameter is re-estimated. An initial estimation error is calculated as the difference between the two estimates. The estimated symbols are weighted using the initial estimation error, and channel decoding is performed. Estimated symbol weights may be reduced when the initial estimation error is above a threshold, and may be increased when the initial estimation error is below a threshold.
Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.
Type:
Grant
Filed:
June 29, 2006
Date of Patent:
March 4, 2008
Assignee:
Intel Corporation
Inventors:
Suwei Chen, Derek M. Conrow, Aaron K. Martin
Abstract: A gain-step transconductor circuit operates with multiple gain values. The gain can be stepped from one gain value to another by selecting a different signal path between an input node and an output amplifier. The output amplifier may operate as a common source amplifier or a common gate amplifier.
Abstract: A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.
Abstract: A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.
Abstract: A mobile station in an 802.11 wireless network dynamically adjusts a number of 802.11 beacon intervals to sleep based on a power savings level and a required wake-up time to receive packets from an access point. The power savings level is based on data traffic activity in a current period. The mobile station wakes up to receive a beacon, and if a beacon is not received, the mobile station sleeps for one additional beacon period.
Abstract: A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
Type:
Grant
Filed:
December 29, 2004
Date of Patent:
September 18, 2007
Assignee:
Intel Corporation
Inventors:
Steven K. Hsu, Ram K. Krishnamurthy, Mark A. Anders
Abstract: A biased transistor circuit utilizes a transistor that exhibits a change in threshold voltage as the drain-to-source voltage changes due to power supply voltage changes. A bias circuit senses the power supply voltage changes and modifies a gate bias voltage on the transistor to maintain a substantially constant drain bias current in the transistor.
Abstract: A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.
Type:
Grant
Filed:
March 31, 2006
Date of Patent:
July 3, 2007
Assignee:
Intel Corporation
Inventors:
Suryaprasad Kareenahalli, Zohar Bogin, Chee Hak Teh
Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.
Abstract: A flash memory file system logically divides at least a portion of the flash memory into memory fragments and headers associated with the memory fragments. The flash memory file system also includes a transaction information structure in support of transacted operations. The transaction information structure includes fields to indicate whether a transaction has begun, whether commitment of the transaction has begun, and whether commitment of the transaction has been completed. File system operations may be rolled back if a transaction was interrupted.
Abstract: A scan enabled storage device includes two storage elements and two input circuits. A data input circuit accepts a data signal, a clock signal, and a scan enable signal to inhibit the operation of the clock signal. A scan data input circuit accepts a scan data signal and a scan clock signal.
Abstract: An oscillator circuit may be operated in a high power mode or a reduced power mode. The high power mode provides fast start-up of the oscillator circuit.
Type:
Grant
Filed:
December 15, 2004
Date of Patent:
October 17, 2006
Assignee:
Intel Corporation
Inventors:
Paul E. Stevenson, Jon E. Tourville, Nathan L. Pihlstrom