Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
Type:
Grant
Filed:
June 30, 2004
Date of Patent:
October 10, 2006
Assignee:
Intel Corporation
Inventors:
Yibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
Abstract: A nonvolatile memory device may include circuitry to support the partitioning of the memory into two or more logical partitions. The two or more logical partitions may be accessible by two or more separate interfaces with different characteristics.
Abstract: A cyclic analog to digital converter (ADC) circuit operates to convert an analog input voltage into a digital output word. The ADC circuit includes an amplifier and capacitors configured as an integrator.
Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
Type:
Grant
Filed:
June 29, 2004
Date of Patent:
September 5, 2006
Assignee:
Intel Corporation
Inventors:
Ali Keshavarzi, Fabrice Paillet, Muhammad M Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H Tang, Mohsen Alavi, Vivek K De
Abstract: A translation look-aside buffer (TLB) has lockable entries. A number of entries to lock may be determined by counting unique page access instances during an active period of a process, determining a value of a page usage metric for the process, and comparing the value of the page usage metric to values of page usage metrics for other processes. The page usage metric may consider many different factors, including the amount of time a process is active, a frequency of invocation of the process, and a priority level of a process.
Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.
Abstract: A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.