Abstract: A fuse for a semiconductor integrated circuit is provided wherein a strip of corrosive material (82), such as aluminum, has one end thereof connected to a conductive strip (84) of a non-corrosive material and the other end thereof connected to a strip (94) of non-corrosive conductive material. The one end of the conductive strip (82) connected to the conductive strip (84) is connected through a contact (88). Similarly, the other end of the strip (82) is connected through a contact (96) to the non-corrosive conductive strip (94). The strips 84 and 94 provide a barrier to corrosion. This occurs whenever a break (104) is formed in the fuse to expose the ends of the fuse (82) at the break to a corrosive atmosphere. Alternatively, the fuse could be connected to corrosive underlying layers with contacts (118) and (124) of non-corrosive material such as a polysilicon or a polyside, or the active region of the substrate itself.

Abstract: A method of forming a planar dielectric layer over an interconnect pattern which requires fewer processing steps and has a lower dielectric constant than is obtained in the prior art. The method comprises providing a substrate having an electrical interconnect pattern thereon, forming a first layer of dielectric over the interconnect pattern, preferably by plasma generated TEOS oxide, forming a porous second layer of silicon-containing dielectric with low dielectric constant different from the first layer over the first dielectric layer from an inorganic silicon-containing composition, preferably hydrogen silsesquioxane and forming a third layer of dielectric different from the second layer over the second dielectric layer, preferably by a plasma generated TEOS oxide.

Abstract: A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.

Abstract: The invention is a single piece deep downset exposed lead frame (10) that can be used in current production processes. A single lead frame (10) has a die mount pad (12) that is formed with a downset or cavity into which the semiconductor die (20) is mounted. Wings (14, 15, 17, 18) lock the die pad in the device package (21) and increase the length of potential moisture paths (34a). The downset die pad (12) provides direct thermal contact of the die mount pad (12) to an external heat sink, eliminating the need for a heat slug internal to the package. The exposed die pad (12) can also be used as an RF ground connection to an RF circuit ground plane.

Abstract: A new signal quantization scheme is proposed which reduces fluctuation of the output signal by a signal quantizer (10) providing a quantized output signal and multiplying (18) said input signal X by a factor (1-w.sub.1)and finding a difference signal .DELTA..sub.in (11) between both the input signal and the previous input signal and multiplying (16) that by a weighting factor w.sub.2 from a control (13). The previous quantizer output signal Q.sub.prev is summed (17) with the weighted difference signal .DELTA..sub.in w.sub.2 and the sum is weighted by a weighting factor w.sub.1 at a multiplier (19) to yield w.sub.1 (Q.sub.prev +w.sub.2 .DELTA..sub.in). This signal is then summed at an adder (21) and applied to the quantizer (10) so that the quantizer is forced to match the fluctuation in the input signal as well as the signal itself.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: In an address transition detection summing circuit, the varying address signal pulse widths can result in output signals from the address transition detection summing circuit which can compromise the performance of the associated memory circuitry. A parallel signal delay path, activated by the leading edge of the address signal, is incorporated in the address transition detection summing circuit and a logic ANDing element so that not only is the signal resulting from the trailing edge of the address signal applied to the logic ANDing element, but the trailing edge signal from the parallel signal delay path must be applied to the logic ANDing element before the trailing edge of the output pulse from the address transition detection summing circuit is generated. In the manner, an address transition always results in an output signal pulse having a preselected minimum width.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: The present invention provides a modular electronic component (10) wherein a sequence: of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).

Abstract: An address transition detector stores a first output signal on an output terminal for a first predetermined period of time in response to an initial edge of an internal address signal pulse. The address transition detector stores a second output signal on the output terminal for a second predetermined period of time in response to the trailing edge of the internal address signal pulse. When the trailing edge of the internal address signal pulse is delayed from the leading edge of the internal address signal pulse by an amount greater than the first predetermined period, then output signal consists of two pulses. When the trailing edge of the internal address signal pulse is delayed from the leading edge by a time less than the first predetermined period, then the signal on the output terminal is a single expanded signal. Typically, the first and second predetermined periods are equal.

Abstract: A graphics display system includes a random access memory arranged with a split serial register and a multiplexer for coupling column of storage cells from the memory array to storage elements of the split serial register. Data stored in either a low half or a high half of the addresses of the memory array may be selectively coupled through the multiplexer to either a low half or a high half of the split serial register. For a tile oriented graphics display operation, this arrangement increases the number of choices of where within the random access memory array to store specific bits of the tile data to be displayed. Data representing a tile can be mapped into a single row of the random access memory array.

Abstract: A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350.degree. C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350.degree. C.-500.degree. C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400.degree. C.

Abstract: An integrated circuit interconnect structure is provided, along with a method of forming the integrated circuit interconnect structure. A semiconductor material layer has an elongate trench formed therein. A conducting region is disposed in the trench. An insulator region overlies the conducting region. One or more contact regions are disposed through the insulator region to contact the conducting region.

Abstract: A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

Abstract: The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which exceeds a preselected amount. The second amplifier operates at a higher power level and provides compensation for transients in the plate voltage resulting from the charging and discharging of the storage cells. Because the transients occur when the storage cells are accessed, the second amplifier is enabled only when a group of storage cells is accessed. In addition to operating at a higher power level, the second amplifier is more sensitive and responds to smaller excursions from the nominal voltage. Both the first and the second amplifiers have separate driver circuits for responding to excursions above and for responding to excursions below the nominal voltage.

Abstract: A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.

Abstract: A memory card has a housing including an interior chamber and a top metal cover. A substrate is located in the interior chamber and carries printed circuit leads, packaged semiconductor devices connected to selected printed circuit leads, and a connector connected to selected printed circuit leads. The packaged semiconductor devices are spaced from the top metal cover and a thermal coupler is located between the top metal cover and the packaged semiconductor devices for coupling heat generated by the packaged semiconductor devices to the top metal cover.

Abstract: An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one another that lie between a first plurality of leadfingers and a second plurality of leadfingers. An electronic device is connected to the first leadframe power supply bus and to the second leadframe power supply bus. Another electronic device can be connected to the first leadframe power supply bus and to the second leadframe bus. Exemplary of the electronic devices are a de-coupling capacitor and a capacitor for high frequency noise suppression. A semiconductor die is attached to the power supply busses. A substance encapsulates the components so that an integrated semiconductor chip is formed. A method of making an integrated circuit device is also disclosed.

Abstract: Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may be filled with a plug of refractory metal before the copper is deposited, or the first refractory metal layer may be conformally deposited to coat the sidewalls of the hole.

Abstract: An infrared imager, wherein an array of detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of averaging capacitors with addressing and output connections, and via holes through (or bump bonding pads on) the HgCdTe are used to connect each detection device to its corresponding averaging capacitor. The signal from each detection device is repeatedly averaged into its averaging capacitor, so that the output of each pixel site is sensed as an average over a number of read cycles which provides a greatly improved signal-to-noise ratio.