Abstract: An infrared imager, wherein a transparent gate is separated from a very narrow bandgap semiconductor (such as HgCdTe) by a thin dielectric. The gate is biased to create a depletion well in a semiconductor, and photo-generated carriers are collected in the well. The gate voltage is sensed to measure the accumulated charge. Preferably the accumulated charge is not sensed directly from the gate, but the gate output is repeatedly averaged with another capacitor, so that the output of the imager is sensed as an average over a number of read cycles, which provides a greatly improved signal-to-noise ratio. Preferably an array of the MIS detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of the averaging capacitors with addressing and output connections, and via holes through the HgCdTe are used to connect each detection device to its corresponding averaging capacitor.

Abstract: The projection display of the present invention employs a light source, a spatial light modulator such as a deformable mirror device having a plurality of individually electrically deformable mirror cells and Schlierin optics to project light from deformed mirror cells onto a viewing screen. An optical system forms light from the light source into a substantially collinear beam. A Schlierin optical device composed of alternating reflecting and transmitting portions is disposed at an angle to this beam. Light reflected or transmitted by the Schlierin optical device is focused by additional optics to a point near the deformable mirror device. Light reflected from undeformed mirror cells passes through the Schlierin optical device back to the light source. Deformed mirror cells reflect light at least in part to differing portions of the Schlierin optical device to follow a different path to a viewing screen.

Abstract: A portable educational device that is adapted to be used in conjunction with a counter (12) having a display (14) and a keyboard (16) for input of data. A memory slot (18) or an alternate port (19) is provided on the computer (12) to receive the educational device (20). Educational device (20) contains a keypad (24) and a display (26) and operates independent of the computer (12). The educational device (20) includes a central processing unit (48), a Read Only Memory (42) and a Random Access Memory (44). A primary power source (54) supplies power to the educational device (20) during the operation thereof. A back-up power source (56) provides power to the Random Access Memory (44) to form a non-volatile memory for retention of data during periods of non-use. A connector (34) interfaces with the computer (12) to allow the computer (12) to address the Random Access Memory (44) to retrieve data stored therein and to store data at selected locations therein for use by the Central Processing Unit.

Abstract: An electronic handheld talking translator including a speech synthesis integrated circuit device. The speech synthesis integrated circuit device includes a digital filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter, a speaker and associated timing circuits. A non-volatile memory stores digital data representative of the correct spellings of selected words in a foreign language and the model vocal tract control data necessary to control the speech synthesis circuit in a manner to cause the selected words to be audibly pronounced by the translator.

Abstract: Method and apparatus for converting voice characteristics of synthesized speech from a single applied source of synthesized speech in a manner obtaining modified voice characteristics pertaining to the apparent age and/or sex of the speaker. The apparatus is capable of altering the voice characteristics of synthesized speech to obtain modified voice sounds simulating child-like, teenage, adult, aged and sexual preference characteristics by control of vocal track parameters including pitch period, vocal tract model, and speech data rate. A source of synthesized speech having a predetermined pitch period, a predetermined vocal tract model, and a predetermined speech rate is separated into the respective speech parameters. The values of pitch, the speech data frame length, and the speech data rate are then varied in a preselected manner to modify the voice characteristics of the synthesized speech from the source thereof.

Abstract: A data processing apparatus having a plurality of preprogrammed functional operations and at least one user accessible memory includes a generalized input sequence for combining functional operations with data storage in one of the user accessible memories. In the case where a number of user accessible memories is provided, memory entry is enabled by a store input followed by an input designating the memory while a memory recall operation is enabled by a recall input followed by a memory designation input. The algebraic memory operation and entry sequence requires entry of the store input, the desired operation input and the memory designation input. If a unary operation is selected, the selected operation is performed on the data stored in the output indicator memory or alternately on the data stored in the designated memory and the result is stored in the designated memory.

Abstract: A formant tracker for receiving an analog speech signal and generating indicia representative of the formant. A pitch tracker determines the fundamental frequency of the analog speech input. The fundamental frequency is used to control a sinusoidal oscillator in the generation of a sinusoidal signal which when combined with the analog speech input generates a convolution over the chosen formant frequency. The process is repeated for each integer multiple of the fundamental frequency, thereby changing the sinusoidal oscillator. The optimal integer multiple is chosen which generates the formant identification. The optimal integer is also used to generate an appropriate bandwidth. Three formant frequency ranges are used to define human speech. The optimal integers for the other two formant identifications and the appropriate bandwidths are similarly determined. The three optimal integer values are combined with the fundamental frequency to get the three formant values and their associated bandwidths.

Abstract: A memory system includes a multiple memory pointer in which a pointer selection signal selects one of a plurality of memory pointers to generate an address signal for application to the memory for controlling the location of memory operations. In the preferred embodiment the memory is arranged in an X by Y matrix having X times Y individually addressable memory locations. A first pointer circuit has a plurality of address pointers, one of which is selected for generation of an X coordinate address. A second pointer circuit includes a single address pointer for generation of the Y coordinate address. The second pointer circuit may be a multiple pointer in an alternative embodiment. By provision of a number of individually addressable memories responsive to the same memory pointer system, separate application of address signals from differing address pointers to differing memories permits multiple memory operations in a single instruction cycle.

Abstract: A handheld electronic learning aid is disclosed. The learning aid is utilized for teaching and testing associations between pictorial representations and the correct responses to the pictorial representations. A selected one of an associated group of numbered printed pictorial representations is randomly selected by the learning aid, and the operator attempts to correctly respond to the pictured object. Scoring functions and displayed reward phrases provide positive reinforcement of learned skills. One embodiment of the learning aid is utilized to teach and strengthen spelling skills in young children. Additionally, anagram or other alphabetic type modes of operation can provide training and experience in literary skills.

Abstract: An electronic teaching apparatus which utilizes interchangeable flexible overlays with printed pictorial representations in conjunction with a programmable keyboard. An integrated circuit speech synthesizer is utilized to verbally ask an operator to select a particular pictorial representation or to verbally identify a pictorial representation selected by the operator. Upon the failure of the operator to correctly select a particular pictorial representation, the verbal request can be repeated in conjunction with a verbal description of some attribute of the desired pictorial presentation. Each of the interchangeable overlays is coded to allow control circuitry to select a proper sequence of words for a given overlay.

Abstract: An improved CMOS frequency divider circuit is disclosed which has override logic for forcing the circuit to exit from a forbidden state to a valid state.

Abstract: A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved.

Abstract: Disclosed is an electronic calculator system having an input for receiving data and command signals, a memory for storing inputted data and data to be outputted, an arithmetic unit for performing arithmetic operations on the data stored in the memory, a first read-only-memory for storing groups of instruction words for controlling the data stored within the memory and for controlling the arithmetic operations performed by the arithmetic unit, a second read-only-memory for storing a set of program codes, each program code being effective for addressing a selected group of instruction words and control circuitry for reading out the groups of instruction words corresponding to an addressed set of program codes.

Abstract: In an N-channel MOS integrated circuit operating in response to a major-major clock having four phases, .phi.1, .phi.2, .phi.3 and .phi.4, each of which has one, but only one, other phase which does not overlap therewith, an improved gate is disclosed wherein a first one of said phases samples an input signal for retention via a capacitive device, a second one of said phases is gated according to the state of the sample retained via the capacitive device, and a third one of said phases enhances the retention of the capacitive device.