Patents Represented by Attorney, Agent or Law Firm Leslie A. VanLeeuwen
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Patent number: 6304983Abstract: A processor register is reserved by early firmware code to be employed for checkpoint logging or for storing diagnostic information at the time of failure before a checkpoint display device, usually contained within an I/O subsystem, is initialized. Early firmware codes are usually written in assembly language and the firmware of the present invention dedicates a processor register for logging checkpoint information. If a machine fails before any checkpoint, or point of failure, is displayed by a checkpoint display device, a dedicated processor register has logged any checkpoint or diagnostic information. The error information relating to the failure is obtained from the dedicated register through JTAG (Joint Task Action Group) scanning utilizing a processor debugging tool.Type: GrantFiled: September 30, 1998Date of Patent: October 16, 2001Assignee: International Business Machines CorporationInventors: Van Hoa Lee, David Lee Randall
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Patent number: 6289303Abstract: A method and system for supporting multiple language sets in a data processing system, where each character of the language set is a pen based input character. A language set is designated among multiple language sets with which a pen-based character is associated within a data processing system in response to a user input. A pen based input character is penned into said data processing system. The pen based input character is identified within only said designated language set. The pen based input character is translated into a graphically displayed iconic representation of the pen based input character represented in a designated language set.Type: GrantFiled: January 29, 1999Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: Steven Atkin, Jonathan Mark Wagner
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Patent number: 6252600Abstract: A computer system has a graphics subsystem employing a rasterizer and a frame buffer, with a digital-to-analog converter for producing drive signals to a video display. A bus interface acts as a gateway between a PCI bus and the graphics subsystem; this interface manages commands and DMAs passing between the host processor and various parts of the graphics subsystem. Within the interface, two command FIFOs are employed, one for storing commands/data sent from the host for 2D display (window management) and another for 3D applications. Using two command FIFOs eliminates the need for host semaphore, FIFO draining, and the latency associated with these operations. Timers are provided in the interface, associated with the two command FIFOs, to manage and regulate the frequency with which the system automatically switches between 2D and 3D FIFO processing. Host intervention is minimized by use of a context macro store for holding locally the sequences for context save and context restore which are used repeatedly.Type: GrantFiled: October 2, 1998Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: Ashu Kohli, Christopher Edward Koob, Thomas P. Lanzoni, James Anthony Pafumi, William Alan Wall, Jeffrey Allan Whaley
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Patent number: 6247015Abstract: A method for compressing files utilizing a dictionary within a data-processing system is disclosed. A binary file commonly available to a data-compressing system during compression and to a data-decompressing system during decompression can be served as a dictionary file. A first dictionary array is initially generated utilizing the dictionary file. Each entry within the first dictionary array includes a set of unique bit patterns from the dictionary file. An input file is parsed into multiple blocks, with each block having the same length as each entry within the first dictionary array. The input file is then compared against the first dictionary array, and each entry within the first dictionary array that includes the same bit patterns as a block from the input file is marked accordingly. A second dictionary array that includes all the marked entries from the first dictionary array is subsequently generated, and this second dictionary array is utilized in the compression of the input file.Type: GrantFiled: September 8, 1998Date of Patent: June 12, 2001Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Nadeem Malik, Steven Leonard Roberts
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Patent number: 6243722Abstract: A method and system in a computer network for assisting users in collectively creating documents with minimal document intrusiveness via the computer network. Initially, a document is displayed in a graphic interface of a computer in a computer network, such that the document may also be displayed at any one of a number of computers within the computer network. Next, portions of the document are designated which may be commented upon by users. These portions of the document are automatically associated with displayable interface wherein users may enter comments pertaining to the document. The displayable interface is then displayed within the graphic interface, in response to user input. A user is then permitted to enter comments pertaining to the document within the displayable interface, such that the comments may be separately stored, subsequently retrieved and utilized in the creation of the document without cluttering.Type: GrantFiled: November 24, 1997Date of Patent: June 5, 2001Assignee: International Business Machines CorporationInventors: Don Rutledge Day, Carl William Romero
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Patent number: 6240430Abstract: Multiple blocks of noncontiguous text displayed in a user interface may be selected by a user and simultaneously manipulated. Actuation of the multiple text selection control by the user creates an array of buffers, with each buffer allocated for one of the noncontiguous blocks of text selected by the user. A paste operation results in the contents of the buffers being concatenated and pasted together as one block. A delete operation results in all selected blocks of text being simultaneously deleted. Other operations may also be performed simultaneously on the multiple blocks of noncontiguous text selected by the user.Type: GrantFiled: December 13, 1996Date of Patent: May 29, 2001Assignee: International Business Machines CorporationInventors: Kevin W. Deike, Hatim Y. Amro
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Patent number: 6237057Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus.Type: GrantFiled: December 16, 1998Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Dan Marvin Neal, Richard Allen Kelley
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Patent number: 6237103Abstract: A data processing system includes a power control circuit, a processor, a power supply, and a plurality of other components. Upon system reset, the power control circuit can generate at least one sequencing signal indicating a first sequence in which power is to be supplied to the plurality of components. Similarly, power sequencing code executed by the processor upon system reset can selectively generate at least one sequencing signal indicating a second sequence in which power is to be supplied to the plurality of components. The power supply, which can receive both the sequencing signal generated by the power control circuit and the sequencing signal generated by the power sequencing code, supplies power to the plurality of components in the second sequence if the power supply receives the sequencing signal generated by the power sequencing code. In one embodiment, the plurality of components require a plurality of different power supply voltages.Type: GrantFiled: September 30, 1998Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Noly Y. Lam, Franklin Mark Liu, Lynn Eugene Simmons
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Patent number: 6237004Abstract: The present invention is a system, method, and computer readable medium for determining which graphic user interface (GUI) control element, including a graphic symbol and associated control code, to use to display particular data. The present invention uses a data-driven model, wherein the GUI control element, referred to as a widget, for a particular set of data is determined dynamically, based on information contained in a database. A widget may be created, displayed, and modified without having to change the program code which uses the widget to display data. As a program executes, it is determined that data needs to be displayed as part of a graphical user interface. The program which is executing calls a generic GUI manager, which determines which widget to use for the particular data at this point in the program and displays the widget. The generic GUI manager reads a database entry associated with the data to be displayed. The database entry contains information, or characteristics, regarding the data.Type: GrantFiled: February 24, 1998Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: John Paul Dodson, Minh Nguyen, Chris Alan Schwendiman
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Patent number: 6233636Abstract: Method and system aspects for enhancing a peripheral component interconnect (PCI) bus to achieve higher frequencies of operation are described. A system aspect includes at least one source synchronous strobe line for providing a source synchronous strobe signal, and at least one PCI compliant device for driving the source synchronous strobe signal to clock data and address on and off a PCI bus, wherein a cycle time for data transactions is reduced. With the present invention, significantly higher frequency capability of PCI is enabled by defining a different clocking signal and protocol for clocking data on and off the bus. A very significant timing budget savings results through the use of a source synchronous strobe for clocking data. Cycle time for bus transactions is therefore reduced, so that the frequency of operation for a synchronous bus is increased.Type: GrantFiled: December 3, 1998Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Richard Allen Kelley, Danny Marvin Neal, Kenneth A. Riek
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Patent number: 6229779Abstract: A physical play-in-place case for housing and playing a media disc, such as an audio compact disc (CD). The case comprises a base, a shell attached to the base defining a cavity for receiving a CD, the shell further having a landing portion defining a spine area extending substantially along a common side of the base and the shell, and a cover hinged to the base along the spine area. Playback controls are located at the landing portion of the shell and extend into the spine area. At least one audio output device is located in the shell. A track/time display can also be located at the landing portion of the shell. In a further embodiment, a graphic display panel is attached to the cover, and may be viewed when the cover is in the closed position. A touch screen may be operatively combined with the graphic display panel. The case can be fabricated in the same size as conventional CD jewel cases, i.e., with dimensions no greater than about 14 cm×12.5 cm×10 cm.Type: GrantFiled: June 29, 1998Date of Patent: May 8, 2001Assignee: International Business Machines CorporationInventors: Richard Edmond Berry, Scott Anthony Morgan, John Martin Mullaly, David John Roberts, Craig Ardner Swearingen, Anthony Christopher Courtney Temple
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Patent number: 6230121Abstract: A method of monitoring an individual's interactions, by recording a value of an interaction parameter of the individual (such as conversational speech) using a measurement device, storing the value of the interaction parameter with an associated geographic coordinate, and generating a report, including the value of the interaction parameter and the associated geographic coordinate. The report can further include a timeframe associated with the particular value of the interaction parameter. The global positioning system (GPS) can be used to provide the geographic data. The directional orientation (attitude) of the individual may further be measured and used to facilitate selection of one or more other subjects as recipients of the communication (i.e., when the individual is facing one or more of the subjects).Type: GrantFiled: March 30, 1998Date of Patent: May 8, 2001Assignee: International Business Machines CorporationInventor: Owen Wayne Weber
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Patent number: 6230265Abstract: A data processing system includes a plurality of components, a power control network, processing resources, and a memory that contains initialization firmware. At system startup, the power control network initiates supply of power to the plurality of components and collects information regarding which components are supplied power. In addition, the initialization firmware initializes the plurality of components to establish a configuration. If an ambiguity in the configuration arises, the initialization firmware resolves the ambiguity utilizing the information collected by the power control network.Type: GrantFiled: September 30, 1998Date of Patent: May 8, 2001Assignee: International Business Machines CorporationInventors: George Henry Ahrens, John C. Kennel, Jayeshkumar M. Patel, Kurt Paul Szabo
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Patent number: 6226720Abstract: Memory bank pairs are sorted utilizing variables determined by a scoring criteria. The scores for the variables are based on the number of memory blocks in a memory bank that are filled; the total number of memory bank pairs that are identically populated (same set of blocks per bank) and the number of memory bank pairs that either match or are close to a standard interleave value. Sort schemes are determined by the values of each variable. A first sort scheme is attempted and after the sort scheme is complete, if all possible configurable banks are not configured, the banks are marked un-configured and another sort scheme is tried. Each sort scheme, utilizing a maximum of four schemes, is attempted until a method is found that configures all possible configurable bank pairs. Sorting is done for up to three levels, i.e., all bank pairs are sorted according to a first value, then all bank pairs with equal values are sorted according to a second value.Type: GrantFiled: December 11, 1998Date of Patent: May 1, 2001Assignee: International Business Machines CorporationInventors: Daniel James Henderson, James Otto Nicholson, John Hughes Rost
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Patent number: 6226739Abstract: A method and computer program is provided whereby a personal digital assistant or personal palm-type device of very limited RAM capacity can make available sufficient RAM capacity to store a complete global software distribution package so that the appropriate software or software upgrade may be installed into the device from the global package. The method includes the steps of: first deleting from the personal palm-type device RAM all application programs other than application programs required to support the device operating system to receive the global software distribution package and loading the received global software distribution package into the now available device RAM. Then, the software from the global package needed to make the distribution or upgrade of the device is loaded from the global distribution package into the device programmable ROM where all of the device software is permanently stored.Type: GrantFiled: December 14, 1999Date of Patent: May 1, 2001Assignee: International Business Machines CorporationInventor: Brian Lee White Eagle
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Patent number: 6223142Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.Type: GrantFiled: November 9, 1998Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: John Fowler Bargh, Wolfgang Roesner, Derek Edward Williams, Bryan R. Hunt
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Patent number: 6222561Abstract: To reduce the performance penalty associated with frame buffer memory access times for each page when rendering a primitive having scan lines which cross page boundaries, rendering is constrained to a single page at a time. All pixels mapping to a currently-cached frame buffer page are rendered before loading a different frame buffer page into the cache in order to render other pixels within the primitive. Any pixels within a scan region which map to a different page than the active page are temporarily skipped until all pixels mapping to the current page are completed. Only when no more pixels require rendering within the primitive which map to the currently active frame buffer page is another frame buffer page loaded and all pixels mapping to that page are rendered. In processing a scan region which crosses a page boundary, the next pixel or pixel group to be rendered is examined to determine if it maps to the currently active frame buffer page.Type: GrantFiled: September 17, 1998Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventor: Kenneth William Egan
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Patent number: 6219828Abstract: A first copy of Open Firmware is loaded into system memory to supply a debug function and a second copy of the same firmware is then loaded to provide functional code which is to be debugged. The first copy of Open Firmware in system memory is designated as the resident debugging function. Kernel code, within the first copy, sets up an executing environment for the debugger, such as system exception handlers and debug console enablement. Normal Open Firmware configuration variables are retrieved from Non-Volatile Random Access Memory (“NVRAM”) by the first copy and transmitted to the loader. The second copy of Open Firmware is loaded into system memory to a location specified by the configuration variables. The second copy firmware image is designated as a normal Open Firmware operation in the system. The second copy initially takes over all system exception handlers except instruction breakpoint exception, program interrupt exception and trace exception.Type: GrantFiled: September 30, 1998Date of Patent: April 17, 2001Assignee: International Business Machines CorporationInventor: Van Hoa Lee
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Patent number: 6216226Abstract: A method and system for faster initial program loads by normally booting a data processing system without extended diagnostic tests is disclosed. A service processor is provided and located within the data processing system to monitor the data processing system during runtime operations for a system failure. When a system failure occurs, the service processor enables a diagnostic flag located in non-volatile memory. On the first or next boot of the data processing system after repair of the system failure, the diagnostic flag indicates to the service processor to perform an extended diagnostics test. Upon completion of the extended diagnostics test, the diagnostic flag is disabled and the service processor once again monitors the data processing system for a system failure.Type: GrantFiled: October 2, 1998Date of Patent: April 10, 2001Assignee: International Business Machines CorporationInventors: Salim Agha, Chetan Mehta, Maulin Ishwarbhai Patel
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Patent number: 6212491Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.Type: GrantFiled: November 9, 1998Date of Patent: April 3, 2001Assignee: International Business Machines CorporationInventors: John Fowler Bargh, Bryan Ronald Hunt, Wolfgang Roesner, Derek Edward Williams