Abstract: Memory bank pairs are sorted utilizing variables determined by a scoring criteria. The scores for the variables are based on the number of memory blocks in a memory bank that are filled; the total number of memory bank pairs that are identically populated (same set of blocks per bank) and the number of memory bank pairs that either match or are close to a standard interleave value. Sort schemes are determined by the values of each variable. A first sort scheme is attempted and after the sort scheme is complete, if all possible configurable banks are not configured, the banks are marked un-configured and another sort scheme is tried. Each sort scheme, utilizing a maximum of four schemes, is attempted until a method is found that configures all possible configurable bank pairs. Sorting is done for up to three levels, i.e., all bank pairs are sorted according to a first value, then all bank pairs with equal values are sorted according to a second value.

Abstract: To reduce the performance penalty associated with frame buffer memory access times for each page when rendering a primitive having scan lines which cross page boundaries, rendering is constrained to a single page at a time. All pixels mapping to a currently-cached frame buffer page are rendered before loading a different frame buffer page into the cache in order to render other pixels within the primitive. Any pixels within a scan region which map to a different page than the active page are temporarily skipped until all pixels mapping to the current page are completed. Only when no more pixels require rendering within the primitive which map to the currently active frame buffer page is another frame buffer page loaded and all pixels mapping to that page are rendered. In processing a scan region which crosses a page boundary, the next pixel or pixel group to be rendered is examined to determine if it maps to the currently active frame buffer page.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

Abstract: A first copy of Open Firmware is loaded into system memory to supply a debug function and a second copy of the same firmware is then loaded to provide functional code which is to be debugged. The first copy of Open Firmware in system memory is designated as the resident debugging function. Kernel code, within the first copy, sets up an executing environment for the debugger, such as system exception handlers and debug console enablement. Normal Open Firmware configuration variables are retrieved from Non-Volatile Random Access Memory (“NVRAM”) by the first copy and transmitted to the loader. The second copy of Open Firmware is loaded into system memory to a location specified by the configuration variables. The second copy firmware image is designated as a normal Open Firmware operation in the system. The second copy initially takes over all system exception handlers except instruction breakpoint exception, program interrupt exception and trace exception.

Abstract: A method and system for faster initial program loads by normally booting a data processing system without extended diagnostic tests is disclosed. A service processor is provided and located within the data processing system to monitor the data processing system during runtime operations for a system failure. When a system failure occurs, the service processor enables a diagnostic flag located in non-volatile memory. On the first or next boot of the data processing system after repair of the system failure, the diagnostic flag indicates to the service processor to perform an extended diagnostics test. Upon completion of the extended diagnostics test, the diagnostic flag is disabled and the service processor once again monitors the data processing system for a system failure.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.

Abstract: A network of a server and a plurality of client computers for small businesses which is easy to install, configure and operate and still provides all of the users in the business with the same transparent access to all of their allocated software resources through a same graphical user interface irrespective of which one of the client computers in the network they may sign onto. The operating systems and the application programs to be used on the client computers are loaded on the server. The users have been prompted for the one time input of data required by the server computer to allocate an operating system and application programs for use by each of a plurality of users on each of the plurality of client computers.

Abstract: To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.

Abstract: A system is provided for setting up what is in effect a “plug and play” local area network for small businesses comprising a server computer and a plurality of client computers. The server computer is preloaded with a network operating system, an operating system for each of the client computers and substantially all application programs to be used by the client computers. There is a programmed interactive display interface in the server computer for interactively prompting a user to make a sequence of data entries relative to the computing needs of the client computers and the users of the client computers. The server computer is then physically interconnected with the client computers. Then means in the server computer allocate the client operating systems and the application programs as needed by the user of the client computers based upon the set up resulting from the prompted data entries.

Abstract: A method and system in a multimedia computer system for automatically retrieving and presenting data associated with an audio recording having unique identifying indicia therein. In response to playing an audio recording in a multimedia computer system, a unique identifying indicia associated with the audio recording is identified. A listing of codes within the multimedia computer system is automatically searched to find a code corresponding to the unique identifying indicia. In response to finding the code corresponding to the unique identifying indicia, multimedia data is retrieved which corresponds to the unique identifying indicia. The multimedia data can be retrieved from local storage or from a remote network site. The multimedia data corresponding to the unique identifying indicia is then presented in the multimedia computer system, while playing the audio recording in the multimedia computer system.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, an instrumentation entity is described utilizing the same hardware description language. Thereafter, the design entity is instantiated in at least one instance within a simulation model of a digital circuit design. Finally, the instrumentation entity is associated with the design entity utilizing a non-conventional call, such that the instrumentation entity may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.

Abstract: A circuit is disclosed that includes a latch circuit and boundary scan cell circuitry. The latch circuit includes a slave latch and a master latch having a data output. The slave latch includes at least a first data input connected to the data output of the master latch, a second data input, and a control input that receives a control signal that controls latching of data present at the second data input. The boundary scan cell circuitry is connected to the second data input and to the control input of the slave latch so that the boundary scan cell circuitry can supply the control signal and data to the slave latch. In one embodiment, the boundary scan cell circuitry is IEEE1149.1-compliant and the circuit further includes either an output driver coupled to the data output of the slave latch or an input receiver coupled to a data input of the master latch.

Abstract: A method and apparatus of a computer based security system to prevent unauthorized access to computer-stored information comprising several components. These comprise of an intrusion detection mechanism, a ROM-based firmware program, an internal battery sized to provide several minutes of operation of the computer system and all its internal devices, and a mechanism to reset the central processing unit of the computer and switch to battery power responsive to the intrusion detection mechanism.

Abstract: A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

Abstract: A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.

Abstract: A method and implementing network computer system is provided in which completion point file positions of multimedia file presentations may be saved in persistent memory devices when a user desires to terminate a multimedia file being presented on a display device. In subsequent network and multimedia file accesses, a user is selectively able to begin play at the previously saved completion point in the multimedia file presentation, i.e. the file position at which the user had previously terminated play. The saved position in one example may include a refresh rewind of a predetermined length from the saved position to refresh a user with the content of the multimedia file being continued. In an exemplary embodiment, a user is also presented with a selection device by which the user may create a title for one or more saved files and corresponding completion points within each saved file. A default file designation may be automatically entered by the program.

Abstract: The present invention allows a multimedia session to be transferred from one application server to another in the event that the original application server fails, and also allows a session to be cooperatively transferred from one application server to another, even though the original application server is still available for use. The new application server may be in the same multimedia computer (i.e. the same physical machine) as the original application server, or the new application server may be in a different computer. The session is transferred without losing existing resources, and callbacks that occur during the session takeover process are not lost. An application server which owns a multimedia session may enable that session for takeover, by using an Application Programming Interface (API). The API returns session takeover data which must be available to a new application server in the event of a takeover.

Abstract: The present invention provides a system and method for organizing objects managed within a desktop. A user may choose to create organizer objects to track and organize any type of object, or even to track and organize particular objects. The method of the present invention allows a user to create an organizer object within any container object on the desktop. An organizer object is a permanent and persistent object which tracks and organizes objects within the container as the objects are selected by the user. When an object of the tracked type is selected by the user, the desktop event handling mechanism notifies the appropriate organizer object. At any time, the user may choose to see the objects as they are organized by an organizer object. Desired objects are found with a minimal amount of effort by the user, and the user may customize the viewing and management of the list of tracked objects, or may choose to use system defaults for the viewing and management of the list of tracked objects.