Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.

Abstract: An apparatus and method for enhancing the security of a cluster box unit which includes a protective enclosure, internal cabinetry, door, hinge and locking system. The cluster box unit may also include outgoing mail compartment doors that are heavily constructed and rigidly reinforced, with the locks carried thereon protectively shielded, and with the extensible bolts of these locks being engaged by brackets that not only lock the outgoing mail compartment doors but also the master loading doors of the cluster box units. The cluster box unit may also include master loading doors are provided with hinges that extend the full height of the doors—hinges that are defined by pivotally interfitting elements of extrusions that very sturdily mount the master loading doors, that prevent prying or bending the doors in the vicinities of their hinges.

Abstract: A card game and video gaming system includes a matrix of card positions in addition to cards dealt for a player's hand. The player may select betting lines or line paths in the matrix to play and set a wager for the selected line paths. Line paths may include a variety of line configurations including rows and/or columns of the matrix. One or more cards may be selected for retention from the player's hand and combined with cards in each of the selected line path of the matrix to form patterns. The matrix may activate card positions or cards depending on line path selections as well as a number of cards selected for retention. A payout may be determined based on the number of patterns formed as well as the type of patterns.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

Abstract: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.

Abstract: Apparatus and methods consistent with the present invention provide for processing mailpiece information in a mail processing device using sorter application software. In one embodiment, a mail processing device uses the sorter application software to communicate with an identification code server. In this embodiment, different types of mail processing devices can use the common sorter application software to communicate with the same or different identification code servers.

Abstract: An intra-convertible thermal vapor extraction and delivery system comprising: an ergonomically-shaped casing comprising a heating element, a fan, an output nozzle thermally coupled to the heating element and having a nozzle base and a tapered nozzle end, and a nozzle sleeve; and a cradle having a bottom surface and a top surface, wherein bottom surface is substantially planar, and top surface is substantially concave so as to accept and securely hold the casing, wherein the fan is positioned substantially behind the heating element so as to blow ambient air through the element, heating it to a desired temperature, and forcing it through the output nozzle, and wherein the nozzle base is positioned to receive the air before the tapered nozzle end, and the nozzle base has a greater outer diameter than the tapered nozzle end, creating a step at the transition between the nozzle base and the tapered nozzle end.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: In a readout bus architecture having a first column, a readout means is coupled to a photodetector and configured to transfer charge from the photodetector. A select means is coupled to the photodetector and is configured to transfer charge from the photodetector. An address circuit is coupled to the first column through the select means and is configured to generate and decode an address and turn on the select means for the first column if the address matched the first column and if the address circuit received a corrected enable signal indicating that the first column is not defective. A correction circuit is coupled to the address circuit and is configured to generate the corrected enable signal indicating that the first column is not defective if the correction circuit determined that the first column is not defective.

Abstract: A stack system and method for in-line geothermal and hydroelectric generation from recovered natural gas-fired water/steam process waste heat. The stack system and method is a new way of reusing natural gas fired water/steam process waste heat to make more electricity from the same Btu inputs. The stack system and method uses warm industrial demineralized water from various sources, a micro-managed combined stack flue system and specific terrain to ring out every bit of energy possible from traditional, heretofore, acceptable wastes. The stack uses two marginal waste heat sources to make one significant heat source for additional fossil fuel-free generation. This stack is unique in that it incorporates tandem, geothermal and hydroelectric generators. The stack can be applied to closed-loop (Power Stack) and open-loop (Desalination Stack) processes.

Abstract: A method for evaluating the compliance of software to a standard quality process includes establishing a standard quality process that includes a plurality of stages, each of the plurality of stages corresponding to a software development process. A plurality of objective qualifiers associated with the standard quality process are defined, and a weighting factor is assigned to each of the plurality of objective qualifiers. The method also includes applying each of the plurality of objective qualifiers to a software application, and determining a field worthiness score corresponding to the correlation of the software application with each of the objective qualifiers.

Abstract: A shield support for underground mining has a slider and a roof bar between which a ram is arranged, with an inclination detector being provided with which the inclination of the roof bar can be measured.

Abstract: A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.

Abstract: An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.

Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.

Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.

Abstract: A method of making a treating wash includes mixing brass granules with acetone, mixing carbon nanotube material, iron pyrite granules and copper granules in the acetone brass mixture, and straining the liquid from the remaining solid material. Methods of treating materials such as brass granules, iron pyrite granules, carbon nanotube material, and brass granules comprises washing the materials in the treating wash, followed by straining and drying the materials.