Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

Abstract: A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

Abstract: A method and a device for preparing a drinking glass, cup, mug or other beverage container, e.g. drink-ware, where any dry granular, flaked, shaved or powder substance (SPICE) is applied to the rim of the drink-ware. Where the drink-ware is inverted and introduced into the SPICE and in order to adhere the SPICE to the rim of the drink-ware, the rim is customarily first moistened with a liquid, gel or other viscous aqueous wetting substance (moistening agent). The dispenser is an all encompassing system to accommodate common large diameter drink-ware, to moisten the rim of the drink-ware, house the SPICE, preserve the moistening agent and preserve the SPICE by separating the moisture of the wetting agent from the SPICE, providing for drink-ware to be introduced into the wetting agent then into the SPICE and to re-close and secure the device and its contents with a screw or snap-on lid.

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.

Abstract: An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed.

Abstract: Methods and systems for providing a video slot machine game of chance are provided herein. A video slot machine may use M-reels to play an N-reel game, where M>N, or may use any field of play larger than necessary to determine a payout outcome of the game. For example, nine reels may be used to play a multi-line five reel video slot game. The reels may be selected by an N-reel wide frame that slides back and forth over the available reels. In some embodiments, reels on one side of the screen pay at a higher rate than reels on the other side of the screen, or pay rates of reels gradually increase or decrease from one end of the visually displayed reels to the other. Optional bonus modes may take advantage of all M reels, e.g., by sliding the frame across the reels without respinning the reels and recalculating pay lines, by providing free spins with the frame locked in place, and/or by moving the frame to a highest paying position for one or more free spins.

Abstract: A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

Abstract: A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

Abstract: A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group.

Abstract: A video slot game is described that increases a multiplier associated with each active pay line of the game independently of the multipliers associated with other pay lines of the game. Each line multiplier acts to multiply the winnings based on that particular line only. A multiplier for a particular line may be incremented for a current spin based on a wager outcome on that line in an immediately previous spin. A line multiplier may continue to increase as long as the player continues to win on that line. The increased line multiplier may have the side effect of acting as an incentive for a player to keep playing the game of chance, so as not to leave an unused line multiplier for another player. According to one variation, if the player does not win on a particular line, then the multiplier associated with that particular line may revert to a default level.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

Abstract: Disclosed is a flatly designed interior light which is essentially characterized by a centrally arranged hollow profiled support (1) that is disposed between two final parts (15) and is provided with an interior receiving space (17) and exterior reflective surfaces (18,19,20,21) for two fluorescent lamps (2, 3) which adjoin the profiled support (1) and run parallel thereto, and light guiding chambers (6, 7) that are placed on both sides of the profiled support (1), extend to the lateral border of the light, and are closed by the light emission surface (13) facing the room. Preferably, the height of the light, which reaches a maximum in the region of the central profiled support (1), decreases continuously in the direction of the edges (11) of the light until reaching approximately the thickness of the components (8, 9, 10) that form the light emission surface (13) facing the room.

Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.