Abstract: A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines.

Abstract: A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.