Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true. The predicate bit, if any, of the destination register is set to the logical AND of the source registers' predicates. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates. The output predicate is evaluated as the logical AND of the inputs' predicates. An additional bit for each data register, a change in the semantics of the instructions to include predication, and a few additional instructions to save and restore register predicate bits and to specifically set or reset a register's predicate bit are required.

Abstract: A method for providing a priority-based, low-collision distributed coordination function (DCF) in a wireless network is provided. The network includes an access point and a plurality of stations. The method includes receiving at a first station a super-frame from the access point. The super-frame is operable to define a service period for each of the stations. A priority for the first station is determined based on the super-frame. A back-off time is selected for the first station based on the priority.

Abstract: The present disclosure provides a system for providing a security and method of providing an enhanced security booting environment. The system and method includes a basic input/output system (BIOS) stored in memory. The system and method also includes a counter embedded in the memory configured to monitor the number of times each block of the memory has been written. This information could be used with existing error detection mechanisms to improve the ability to detect unintended write operations.

Abstract: A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay through the comparator. The duplicate integrator includes current sources and a capacitor matching and switched in tandem with those within the relaxation oscillator, plus an additional current source, and is selectively switched into connection with the comparator input. By canceling the comparator propagation delay, the oscillator output frequency can be stably controlled through selection of resistive and capacitive values, using cheaper technology and tolerating large temperature, voltage and process variations.

Abstract: A first base station is adjacent to one or more second base stations, and the second base stations are adjacent to one or more third base stations. One or more frequency channels or subframes used by the third base stations are identified by the second base stations, which notify the first base station of the frequency channels or subframes used by the third base stations. The second base stations also notify the first base station of the frequency channels or subframes used by the second base stations. The first base station selects a working frequency channel or subframe based on this information. For example, the first base station may ignore any frequency channels or subframes used by the adjacent second base stations. The first base station may also give priority to the frequency channels or subframes used by the non-adjacent third base stations.

Abstract: An audio selection circuit. The audio selection circuit includes a control/switch circuit having a first input, a second input, and a first output, and a signal detector module configured to detect an audio signal on the second input. If the signal detector detects presence of the audio signal on the second input, the signal detector is configured to transmit a control signal to the control/switch circuit, and the control/switch circuit is configured in response to the control signal to disconnect the first input from the first output and to connect the second input to the first output. Otherwise, the control/switch circuit is configured to connect the first input to the first output and to disconnect the second input from the first output.

Abstract: A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol.

Abstract: A common control channel for base station (“BS”)/consumer premise equipment (“CPE”) communication in areas of overlapping coverage by wireless regional area network (“WRAN”) cells operating on different working channels is disclosed. A common control channel is selected from among the various working channels sensed in each of a plurality of overlapping WRAN cells so as to enable BS/CPE and BS/BS communication. Once chosen, each CPE within the overlapping area communicates with the controlling BS via an enhanced coexistence beacon protocol messages. These messages include timing and other synchronization information.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing radio frequency sensing control and dynamic frequency selection control. A method called Cognitive Dynamic Frequency Hopping that is based on the selective Simultaneous Sensing and Data Transmissions is described. The Cognitive Dynamic Frequency Hopping method is further facilitated by a collision avoidance technique. The described method satisfies both reliable and timely RF sensing for guaranteeing licensed user protection, and QoS satisfaction for services of the dynamic spectrum access systems.

Abstract: A method for communications between neighboring wireless cells such as wireless regional area networks operating according to IEEE 802.22 specifications. The method involves scheduling inter-base station communications for over-the-air connections to allow neighboring base stations to communicate in environments where a single available channel is shared between the neighboring cells or where two or more channels used by two or more neighboring cells. In some embodiments, a bridge system, such as a bridge consumer premise equipment (CPE), positioned in an area of coverage overlap between two cells is used for inter-base station communications, and allocation and scheduling of bandwidth on the utilized channels is performed to provide interference free communications between the base stations. Existence announcements are provided in coexistence time slots and requests for bandwidth such as reserved and additional time slots are transmitted between the base stations using the coexistence time slots.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract: In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node.

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract: A methodology for efficiently copying data is presented. An internal controller RAM is multiplexed between storing existing RAM data such as look up table data) and storing copy back data with respect to a flash memory. The data in the controller RAM is temporarily stored in a free space of the flash memory. The data of the flash memory, which is to be copied, is read from a source page and is stored in the free space of the controller RAM, and from there, the data is written to a destination block of the flash memory. After completion of the copy back operation, the data of the controller RAM that was moved to the free space is retrieved for storage back in the controller RAM.

Abstract: A position sensing apparatus and method, motion control system, and integrated circuit are provided that include a plurality of sensors and a tracking processor. The plurality of sensors includes a linear array of sensors that sense a plurality of features of an object. A spacing between two of the plurality of sensors is substantially smaller than a spacing between two of the plurality of features. The tracking processor samples signals from the sensors, compares the samples to previous samples and calculates a position of the object. The plurality of sensors may include a second linear array of sensors. Centers of the sensors of the second linear array may be offset from centers of the sensors of the first linear array along a longitudinal axis of the plurality of sensors.

Abstract: A touch screen capable of correctly identifying multiple touches employs multiple active line arrays oriented to provide multi-dimensional data. Three arrays of capacitance based active lines are each distinctly oriented to form a plurality of intersections. A first and second array are generally oriented perpendicularly while a third array is oriented to bisect the resulting matrix such that the active lines of the third array also intersect the existing vertices. As a result of a touch each active line array identifies the location of the touch from three distinct directions. Ambiguity from dual touch scenarios existing in dual array systems is removed by providing an additional reference.

Abstract: A subframe structure for a wireless community uses a master common subframe and second master common subframe method to give BSs different priorities to serve overlapping areas in common subframes. The subframe structure and corresponding method can increase overlapping cells' capacity and reduce interference.

Abstract: In a method for providing a program guide in a program receiver, program schedule data is received, wherein the program schedule data associates programs with time slots on a particular channel of a plurality of channels. For a first time slot of a virtual channel, and using the program schedule data, a first program is selected from a first channel available for reception in a first selected time slot. For a second time slot of the virtual channel, a second program is selected from a second channel available for reception in a second selected time slot. In response to a request to display a schedule of programs, a schedule of the virtual channel is displayed, including the first and second programs scheduled respectively in the first and second time slots of the virtual channel.