Abstract: A method for creating and maintaining semi-dynamic frequency hopping communities. Each community is a set of neighboring cells, such as wireless regional area networks (WRANs) according to IEEE 802.22, that follow a protocol defining coordinated frequency hopping operations, e.g., hopping is performed by community members according to a leader-defined hopping pattern rather than to channels selected in the prior operation period. Each community has one leader base station and one or more community member base stations. The leader determines membership, calculates hopping patterns for all members, and distributes the hopping information to the community members. Members provide their neighborhood and channel availability information, e.g., information about their sensing results and channel usage of neighboring WRANs.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing messaging control for dynamic frequency selection. The method of the invention provides an efficient, reliable and flexible messaging mechanism for DFS decision-making that is critical for licensed incumbent protection and inter-system coexistence of dynamic spectrum access systems.

Abstract: A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes at least one hardware scheduler capable of scheduling execution of the plurality of threads by the plurality of processors. The at least one hardware scheduler is capable of scheduling execution of the threads by performing instruction-by-instruction scheduling of the threads.

Abstract: The electrical isolation circuit of the present disclosure includes a switch coupled between the DC power source and the electrical application and a comparator for controlling the switch by receiving inputs from the DC power source and the electrical application. The comparator causes the switch to switch ON when the DC power source has a higher voltage than the electrical application allowing the normal operation of the electrical application. However, when the electrical application has a higher voltage than the DC power source, the comparator causes the switch to switch OFF thereby preventing flow of current from the electrical application to the DC power source.

Abstract: A method of controlling the velocity of a voice coil motor (VCM), including sensing a voltage difference between the VCM and a sense resistor and driving a velocity control loop (VCL) based on the voltage difference. There is also a control loop circuit, including a current output connected to drive a voice coil motor, the voice coil motor producing a back electromagnetic field (BEMF) voltage. The circuit also includes a sense resistor connected to the BEMF output, and a BEMF resistive network comprising a first resistor and a second resistor. The circuit also includes a velocity control loop (VCL) connected to control the voltage output according to a voltage difference between (i) a junction of the sense resistor and the current output and (ii) a junction of the first resistor and the second resistor.

Abstract: Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.

Abstract: Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Abstract: A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A method includes identifying a pair of image data blocks separated by a boundary. The image data blocks include image information defining multiple pixels in at least one image. The method also includes identifying at least one filter length based on edge contents of at least some of the pixels in the at least one image. In addition, the method includes filtering at least some of the pixels in the pair of image data blocks along the boundary using the at least one identified filter length.

Abstract: The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, in a preferred embodiment, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.

Abstract: A device and method for generation of a dynamic focus correction signal for use with a CRT that includes an analog scanning processor for generating a dynamic focus correction signal that is proportional to Kx2+(1?K)x4, where x is the distance from a mid point of a viewing surface of the CRT, and K is a real number in the range 0.00 to 1.00. Embodiments of the invention find particular use in CRTs having generally flatter, squarer configurations.

Abstract: A prototype system having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance, are employed to form a voltage-controlled resistance structure. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.