Abstract: A device for switching a coil between a first state where it is connected between a supply source and the ground through an impedance and a second state where it is connected between an output terminal and the ground, a first switch (T.sub.REC) being arranged between the output terminal and the supply source. This switching device comprises: a diode (14) connected between the output terminal (16) and the supply source, a controlled switch (T.sub.PB) connected in parallel with the impedance between a second terminal of the coil and the ground, and a detection and control means (20, 24) connected between the diode and the power supply source for detecting the time when the voltage between the diode and the ground becomes equal to a predetermined value lower than the forward voltage drop across the diode and for thereby controlling said switch.

Abstract: In a spring element according to the present invention, all channels formed in the elastomer block are mutually parallel and all cavities formed in the elastomer block, too, which are intersected by said channels, are arranged like a cubic-free-centered sphere packing in reverse order. Comprising a good mechanical lateral rigidity, a spring element according to the present invention shows exceptionally good acoustic insulating and damping facilities.

Abstract: An electrically programmable non-volatile memory comprises floating gate MOS transistors (T11, T12, T13) and an array of word lines (LM1 and LM2) along rows and bit lines (LB1, LB2 and LB3) along columns. A constant-potential line (B), arranged along a column so it is positioned between a pair of bit lines, connects the source electrodes (22) of the transistors, and includes a first conductivity type diffusion. A drain electrode (21) of the first conductivity type of each transistor extends along a column to form one of the bit lines (LB1, LB2, LB3). An insulating area (24) extends along a column on the side of each bit line opposite a constant-potential line (B). A conductive area (E) corresponding to the floating gate level covers insulating area (24).

Abstract: An angular rate sensor has a tuning fork structure composed of vibratory components. The vibratory components include piezoelectric drive and detection elements which are joined together into a tuning fork configuration, the drive and detection elements lying in respective orthogonal planes. Leads are electrically connected to the drive and detection elements, and lead terminals are electrically connected to the leads, respectively. The vibratory components are covered with a coating which is of a material having a lower elasticity than the elasticities of the vibratory components. The coating on the vibratory components effectively reduces the propagation of unwanted vibrations, thereby reducing output signal drifts.

Abstract: An adsorptive separation process of the present invention relates to a process for separating hydrogen and/or helium by a pressure swing adsorption process using four or more adsorbent beds. Each adsorbent bed manipulates the individual steps of adsorption, equal depressurization, cocurrent depressurization, countercurrent depressurization, purging, equal pressurization, product pressurization and raw gas pressurization while sequentially switching them and carries out the raw gas pressurization step for applying pressure with raw gas as the final step for pressuring the adsorbent bed to the adsorbent pressure. Accordingly, a variation in pressure and flow rate can be suppressed, product can be attained stably, and the amount of product can be increased.

Abstract: Characteristic features of images of an object eye are extracted to enable non-contact detection of eye movement. Two images of the eye are focused, and a differential image is generated to eliminate background noise and to permit feature extraction to be performed. In one feature of the invention, the illuminating light is polarized for use as a reference and the reflected light is separated to two light paths, each of which is focused to form an image of the object. In one path a polarizing plate blocks the regularly reflected light from the cornea so that only a diffused reflection component of the illuminating light from the other parts of the eye is passed, while in the other path both the regularly and diffusedly reflected light components are passed. A resulting differential image emphasizes the regular reflection component from the cornea relative to the background.

Abstract: An internally-chilled piston for an internal combustion engine is provided. This piston comprises a piston body made of an aluminum alloy and a piston head including a cylindrical member and a ring-shaped member engaging the outer peripheral surface of the cylindrical member by a shrink fit bonding. The cylindrical member constitutes the central portion of the piston head, while the ring-shaped member constitutes the periphery thereof. On the surface of the ring-shaped member which contacts with the melt forming the piston body during casting, an aluminized layer is formed which chemically connects the ring-shaped member and the piston body to increase the mechanical strength of bonding therebetween.

Abstract: A substrate is exposed to a gas of reactive material and an oxidizing gas. The oxidizing gas includes an ozone gas. A laser light beam is applied to the substrate through the reactive material gas and the oxidizing gas. The laser light beam activates the oxidizing gas. The activated oxidizing gas reacts with the reactive material gas to form an oxide deposited on the substrate.

Abstract: A testing circuit for a semiconductor memory device is provided. An AND operation is performed on the data read out from each block of a memory cell array when the bit data written into each block of the memory cell array for testing is "1", and a NOR operation is performed on the data read out from each block of the memory cell array when the bit data written into each block of the memory cell array is "0". In this manner, even when the data read out from the blocks are all inverted in their logical states through error, such error can be detected.

Abstract: An encoder encodes input data into codes and outputs the codes. The numbers of bits required to represent the codes which are outputted from the encoder during respective first predetermined periods (such as periods for scanning a block of pixels) are predicted. The predicted numbers are added to derive a sum therefore. Such a sum is generated during each of a plurality of second predetermined periods (such as one-frame periods), which are longer than each of the first periods. An actual number of bits required to represent the output codes from the encoder is controlled in accordance with the derived sum. Differences between the predicted numbers of bits representing the output codes and the actual numbers of bits representing the output codes which are generated during the respective first periods are sequentially generated. The differences are accumulated into an accumulated value.

Abstract: A projectile is accelerated through a barrel by a high pressure hydrogen gas jet that is derived by exothermically reacting water or a water-hydrogen peroxide liquid mixture with metal or a metal hydride. The temperature of the reaction is controlled by controlling the power in a plasma discharge applied to a reaction chamber containing the liquid and particles of the metal or metal hydride. A non-vaporous metal oxide resulting from the reaction is centrifugally separated from the hydrogen that drives the projectile.

Abstract: A projectile is accelerated in a bore of a barrel by applying a plasma to the bore behind the projectile. The plasma has a tendency to occupy a volume in the bore behind a location in the bore where the plasma is applied. A magnetic field is applied to the plasma synchronously with application of the plasma to the bore for substantially preventing the plasma from flowing into the bore volume behind the location.

Abstract: An optoelectronic integrated circuit including an optical bistable circuit comprises: an optical gate device responsive to a current injected to an active layer thereof and to a first ray transmitted through the active layer for emitting first and second light rays and for controlling intensity of the first light ray in accordance with the current; and a first phototransistor serially connected with the optical gate device so arranged to receive the second light ray for causing the current to flow through the optical gate device in response to the second light ray and a set signal light ray, the first phototransistor holding flowing of the current when the second light ray is emitted. This circuit can control the first light ray incident to the optical gate device in response to a set signal light ray applied to the first phototransistor. A second phototransistor may be included for stopping emission of light by the optical gate device in response to a reset signal light ray.

Abstract: A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).

Abstract: Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

Abstract: A semiconductor memory comprises a semiconductor substrate (1), word lines (200) and bit lines (3a, 3b), memory cells and sense amplifier (SA). The semiconductor substrate (1) has a major surface. The word lines (200) and bit lines (3a, 3b) intersect each other on the major surface of the substrate (1). The bit lines (3a, 3b) are arranged in the form of parallel bit line pairs. The memory cells are arranged at intersections of the word lines (200) and the bit lines (3a, 3b). The sense amplifier (SA) senses voltage differentials of the bit line pairs. Corresponding sections of the bit lines (3a, 3b) of the bit line pair are interchanged laterally on the substrate (1) along the length of the bit line pair. Corresponding sections of the bit lines (3a, 3b) of each bit line pair have the same number of joining portions (10) respectively. It is possible to provide a semiconductor memory device having a wiring structure capable of minimizing an influence due to the noise from the adjacent wiring line.

Abstract: In a process for manufacturing MOS-type integrated circuits which comprise memory floating gate transistors and logic transistors, sandwiches comprising a polysilicon level, an isolation layer, an additional polysilicon level and an additional isolation layer are formed at the position of the memory area. At the position of the logic transistors, the additional polysilicon level is present. An additional isolation layer is deposited on the whole circuit. The substrate is anisotropically etched and there remains in the additional isolation layer, in the memory area, lateral regions which form with the isolation layer an isolating encapsulation around each sandwich and, in the logic transistors area, spacers.

Abstract: Waxy barley grain is processed by a series of processing steps to produce beta-glucan solids, a bran residue, a protein concentrate, barley oil and a maltose syrup in uncontaminated form. The process involves steps of mixing a meal produced from waxy barley grain with water, separating barley solids and a water extract, heating the water extract and separating coagulated protein and beta-glucan solids, mixing the barley solids with water and separating a bran fraction and crude starch, forming a dough from the crude starch and separating gluten and waxy barley starch from the dough, mixing the bran fraction with water and enzymes to carry out starch conversion and produce a liquid mixture, separating solids from the liquid mixture, extracting the solids with alcohol to produce oil and recovering maltose syrup from liquid remaining after separating the solids.

Abstract: An ion implantation method comprising doping a trench sidewall formed in the surface of a semiconductor substrate, with impurities by intermittently rotating step ion implantation carried out in the state that said sidewall is angled with respect to an ion beam, wherein;the amount of ion implantation to said sidewall is made uniform by varying the scanning velocity of the ion beam on the surface of said semiconductor substrate, at the position near to, and the position distant from, the upstream side of the beam applied to a position at which said surface of semiconductor substrate is inclined with respect to the beam.Also disclosed is a method of manufacturing a semiconductor device making use of such an ion implantation method.

Abstract: A logic circuit includes an output pull up npn bipolar transistor (15; 28; 38), an output pull down pnp bipolar transistor (16; 29; 39), a first insulated gate type transistor (11, 12; 21, 22, 23, 24; 31, 32, 33, 34) for controlling the base potential of the output pull up bipolar transistor in response to an input signal, a second insulated gate type transistor (14; 25, 26, 27; 35, 36, 37) for controlling the base potential of the output pull down bipolar transistor in response to the input signal, and an impedance element (13; 18; 30; 40) for short-circuiting the base and the collector of the output pull down bipolar transistor. The impedance element is separated from the signal input terminal, and is formed by a resistance or an insulated gate type transistor operating in response to the base potential of the pull up transistor. The output pull up and pull down transistors both have collector grounded arrangement.