Abstract: A high speed remote storage controller system for a computer system has cluster nodes of symmetric multiprocessors. A plurality of clusters of symmetric multiprocessors each of has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. Each cluster has an interface for passing data between cluster nodes of the symmetric multiprocessor system. Each cluster has a local interface and interface controller. The system provides one or more remote storage controllers each having a local interface controller and a local-to-remote data bus. A remote resource manager manages the interface between clusters of symmetric multiprocessors. The remote store controller is responsible for processing data accesses across a plurality of clusters and processes data storage operations involving shared memory.

Abstract: A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.

Abstract: A fast simulation method for single and coupled lossy transmission lines is based on triangle impulse responses. The method is used in simulating systems which can consist of large number of lossy transmission lines with frequency-dependent parameters which are placed in a high-speed IC package design.

Abstract: Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

Abstract: The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function.

Abstract: A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC.

Abstract: A clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.

Abstract: An improved pull-down latch circuit is provided for better latch performance. Previous pull-down latch circuit performance is compromised during pull-up operation since weak PFETs are employed to pull up latch nodes. A pull up assist circuit is incorporated to assist weak PFET when latch node is being pulled up. The assist circuit is isolated from latch circuit when latch node is being pull down to guarantee that pull down circuit can overcome pull-up circuit (for correct latch operation).

Abstract: A Data Management System has a plurality of data managers and is of a layered architecture. The system performs with a data manager and with a user input via an API a plurality of process on data residing in heterogeneous data repositories of said computer system including promotion, check-in, check-out, locking, library searching, setting and viewing process results, tracking aggregations, and managing parts, releases and problem fix data under management control of a virtual control repository having one or more physical heterogeneous repositories. The system provides for storing, accessing, tracking data residing in said one or more data repositories managed by the virtual control repository. User Interfaces provide a combination of command line, scripts, GUI, Menu, Web Browser, and other interactive means which maps the user's view to a PFVL paradigm. Configurable Managers include a query control repository for existence of peer managers and provide logic switches to dynamically interact with peers.

Abstract: Disclosed is an apparatus and means for searching a cache directory with full ECC support without the latency of the ECC logic on every directory search. The apparatus allows for bypassing the ECC logic in an attempt to search the directory. When a correctable error occurs which causes the search results to differ, a retry will occur with the corrected results used on the subsequent pass. This allows for the RAS characteristics of full ECC but the delay of the ECC path will only be experienced when a correctable error occurs, thus reducing average latency of the directory pipeline significantly. Disclosed is also a means for notifying the requester of a retry event and the ability to retry the search in the event that the directory is allowed to change between passes.

Abstract: According to the present invention a pad arrangement is provided for applying reworks or engineering changes to an electronic circuits to be formed on the circuit board, the pad arrangement comprising a first signal pad for being electrically connected to a first signal line, a second signal pad for being electrically connected to a second signal line, a ground pad being connected to a ground line provided on the circuit board, and a voltage pad being connected to a supply voltage line provided on the circuit board, whereby the pads are arranged in proximity to each other for facilitating a placement of electronic devices between at least two of the pads.

Abstract: An Address Compare Circuit (1) allows for a large compare function at high speed due to its unique self-timed evaluation clock and bit compare circuits. The address compare circuit can reliably self-time off of the input data which insures proper compare timing with respect to the arrival of two address busses being compared. The HIT evaluation clock is generated by a circuit that has additional control inputs to increase the arrival times of input data, resulting in a greater operating window. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.

Abstract: In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.

Abstract: A method for insertion of inserting printed circuit card into socket connectors which prevents sockets from getting contaminated or damaged during the insertion of a printed circuit card comprises the steps of: inserting a cam for moving a socket connector's contacts outwardly so that they will not make contact with a card's edge when it is inserted between the contacts of the sockets connector as it is inserted, and after the printed circuit card is inserted the printed circuit card moving the printed circuit card until it makes contact with a stop in the socket connector, and after the printed circuit card has contacted the stop in the socket connector, moving the cam to a closed position allowing the printed circuit card to be seated, and seating the printed circuit card by moving it to cause and allow for an amount of wipe to clean the connector's contacts without contaminating or damaging the socket connector's contacts during the insertion of said printed circuit card.

Abstract: A method and apparatus of interconnecting with a system board is presented. A system board having a metal stiffener mounted thereon is provided with an opening in the stiffener to provide access to an area of interest on the system board. A probe test assembly is positioned a the opening and secured to the stiffener when testing is desired to provide access to the pins of the device under test (e.g., a Multi Chip Module (MCM) on the system board). Alternatively, a system enhancement device, such as an MCM or Single Chip Module (SCM) having additional Central Processing Units (CPU's) or other features, may be installed on the system board at the opening in the stiffener to enhance the function of the system board. Another alternate includes an interface assembly positioned at the opening in the stiffener. A cover is positioned at the opening and secured to the stiffener at all other times.

Abstract: A control program agent at a Web server receives a browser request by way of a server side API and fulfills requests as an agent of the browser client. Program capsules are utilized by distributed integration solution (DIS) servers for retrieving, from a database gateway coupled to a plurality of database resources, requested information from multiple data bases, performing calculations, formatting, and other services on the information and reporting results to the web browser or to other locations, in a selected format, as in a display, fax, printer, and to customer installations.

Abstract: A method and apparatus of interconnecting with a system board is presented. A system board having a metal stiffener mounted thereon is provided with an opening in the stiffener to provide access to an area of interest on the system board. A probe test assembly is positioned a the opening and secured to the stiffener when testing is desired to provide access to the pins of the device under test (e.g., a Multi Chip Module (MCM) on the system board). Alternatively, a system enhancement device, such as an MCM or Single Chip Module (SCM) having additional Central Processing Units (CPU's) or other features, may be installed on the system board at the opening in the stiffener to enhance the function of the system board. Another alternate includes an interface assembly positioned at the opening in the stiffener. A cover is positioned at the opening and secured to the stiffener at all other times.

Abstract: The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors.

Abstract: A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.

Abstract: A counterbalancing arrangement for use with a compressive land grid array connector system provides a counterbalancing load element at a side of a system circuit board opposite a back side holding an integrated circuit chip substrate via the connector system. In a first aspect, the counterbalancing load element is a probe template and spacer element providing measurement across to the integrated circuiting. In another aspect, the counterbalancing load element is a mirror image integrated circuit land grid array connector system.